riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Intersynth URL 

Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
This commit is contained in:
Claire Xenia Wolf 2021-06-09 12:42:52 +02:00
parent 0ff4fb1eb3
commit 2d95a7da9c
2 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
backends/intersynth/intersynth.cc
View File

@ -68,7 +68,7 @@ struct IntersynthBackend : public Backend {
log(" only write selected modules. modules must be selected entirely or\n");
log(" not at all.\n");
log("\n");
log("http://www.clifford.at/intersynth/\n");
log("http://bygone.clairexen.net/intersynth/\n");
log("\n");
}
void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) override

2
manual/command-reference-manual.tex
View File

@ -6999,7 +6999,7 @@ a tool for Coarse-Grain Example-Driven Interconnect Synthesis.
only write selected modules. modules must be selected entirely or
not at all.
http://www.clifford.at/intersynth/
http://bygone.clairexen.net/intersynth/
\end{lstlisting}
\section{write\_json -- write design to a JSON file}