riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

manual: fix typo.

This commit is contained in:
whitequark 2020-08-27 16:34:48 +00:00
parent a0177569ac
commit eae88df016
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
manual/CHAPTER_Overview.tex
View File

@ -92,7 +92,7 @@ in different stages of the synthesis.
\section{The RTL Intermediate Language}
All frontends, passes and backends in Yosys operate on a design in RTLIL} representation.
All frontends, passes and backends in Yosys operate on a design in RTLIL representation.
The only exception are the high-level frontends that use the AST representation as an intermediate step before generating RTLIL
data.