mirror of https://github.com/YosysHQ/yosys.git
Cleans up some descriptions and syntax
Now all rules ending in "-stmt" end in eol.
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@ -87,33 +87,35 @@ A comment starts with a \texttt{\textbf{\#}} character and proceeds to the end o
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\section{File}
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A file consists of zero or more designs. A design may be a module, an attribute statement, or an autoindex statement.
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A file consists of zero or more modules, attribute statements, and auto-index statements. All statements terminate in an end-of-line. Because of this, statements cannot contain end-of-lines.
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Note that in general, statements are terminated by an end of line.
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Attributes at the file level are applied to the following module.
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\begin{indentgrammar}{<design>}
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<file> ::= <design>$*$
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<design> ::= <module> | <attr-stmt> | <autoidx-stmt>
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<file> ::= (<module> | <attr-stmt> | <autoidx-stmt>)$*$
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\end{indentgrammar}
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\subsection{Modules}
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A module consists of zero or more module statements.
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Declares a module consisting of zero or more attributes, wires, memories, cells, processes, and connections.
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\begin{indentgrammar}{<module-stmt>}
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<module> ::= "module" <id> <eol> <module-stmt>$*$ "end" <eol>
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\begin{indentgrammar}{<module-body-stmt>}
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<module> ::= <module-stmt> <module-body> <module-end-stmt>
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<module-stmt> ::=
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<param-stmt>
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<module-stmt> ::= "module" <id> <eol>
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<module-body> ::=
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(<param-stmt>
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\alt <attr-stmt>
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\alt <wire-stmt>
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\alt <memory-stmt>
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\alt <cell-stmt>
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\alt <proc-stmt>
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\alt <conn-stmt>
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\alt <cell>
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\alt <process>
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\alt <conn-stmt>)$*$
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\end{indentgrammar}
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<module-end-stmt> ::= "end" <eol>
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\subsection{Signal specifications}
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A signal is anything that can be applied to a cell port, i.e. a constant value, all bits or a selection of bits from a wire, or concatenations of those.
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@ -138,7 +140,7 @@ Declares a connection between the given signals.
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\subsection{Attribute statements}
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Declares an attribute with the given identifier and value for the following non-attribute statement.
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Declares an attribute with the given identifier and value. Attributes at the file level apply to the following module. Attributes within a module apply to the following non-attribute statement.
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\begin{indentgrammar}{<attr-stmt>}
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<attr-stmt> ::= "attribute" <id> <constant> <eol>
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@ -198,14 +200,16 @@ See Sec.~\ref{sec:rtlil_memory} for an overview of memory cells, and Sec.~\ref{s
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\alt "offset" <integer>
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\end{indentgrammar}
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\subsection{Cell statements}
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\subsection{Cells}
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Declares a cell with the given identifier in the enclosing module.
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See Chap.~\ref{chapter:celllib} for a detailed list of cell types.
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\begin{indentgrammar}{<cell-body-stmt>}
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<cell-stmt> ::= "cell" <cell-id> <cell-type> <eol> <cell-body-stmt> "end" <eol>
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<cell> ::= <cell-stmt> <cell-body-stmt> <cell-end-stmt>
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<cell-stmt> ::= "cell" <cell-id> <cell-type> <eol>
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<cell-id> ::= <id>
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@ -214,6 +218,8 @@ See Chap.~\ref{chapter:celllib} for a detailed list of cell types.
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<cell-body-stmt> ::=
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"parameter" ("signed" | "real")$?$ <id> <constant> <eol>
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\alt "connect" <id> <sigspec> <eol>
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<cell-end-stmt> ::= "end" <eol>
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\end{indentgrammar}
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\subsection{Process statements}
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@ -222,22 +228,34 @@ Declares a process with the given identifier in the enclosing module.
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See Sec.~\ref{sec:rtlil_process} for an overview of processes.
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\begin{indentgrammar}{<switch-element>}
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<proc-stmt> ::= "process" <id> <eol> <case-stmt>$*$ <sync-stmt>$*$ "end" <eol>
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\begin{indentgrammar}{<switch-end-stmt>}
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<process> ::= <proc-stmt> <case-body> <sync>$*$ <proc-end-stmt>
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<case-stmt> ::= <attr-stmt> | <switch-stmt> | <assign-stmt>
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<proc-stmt> ::= "process" <id> <eol>
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<switch-stmt> ::= "switch" <sigspec> <eol> <attr-stmt>$*$ <switch-element>$*$ "end" <eol>
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<proc-end-stmt> ::= "end" <eol>
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<switch-element> ::= "case" <compare>$?$ <eol> <case-stmt>$*$
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<case-body> ::= (<attr-stmt> | <switch> | <assign-stmt>)$*$
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<switch> ::= <switch-stmt> <attr-stmt>$*$ <case>$*$ <switch-end-stmt>
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<switch-stmt> := "switch" <sigspec> <eol>
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<switch-end-stmt> ::= "end" <eol>
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<case> ::= <case-stmt> <case-body>
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<case-stmt> ::= "case" <compare>$?$ <eol>
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<compare> ::= <sigspec> ("," <sigspec>)$*$
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<sync> ::= <sync-stmt> <update-stmt>$*$
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<sync-stmt> ::=
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"sync" <sync-type> <sigspec> <eol> <update-stmt>$*$
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\alt "sync" "always" <eol> <update-stmt>$*$
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\alt "sync" "global" <eol> <update-stmt>$*$
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\alt "sync" "init" <eol> <update-stmt>$*$
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"sync" <sync-type> <sigspec> <eol>
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\alt "sync" "always" <eol>
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\alt "sync" "global" <eol>
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\alt "sync" "init" <eol>
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<sync-type> ::= "low" | "high" | "posedge" | "negedge" | "edge"
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