riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
13,444 Commits 81 Branches 48 Tags 63 MiB
Commit Graph

13444 Commits

Author SHA1 Message Date
Miodrag Milanovic f536de0e0e Verific support for VHDL 2019 2024-03-28 13:21:55 +01:00
Martin Povišer bc087f91ed techmap: Fix using overwritten results in Kogge-Stone 2024-03-27 18:32:25 +01:00
Martin Povišer c49d6e7874 techmap: Add Kogge-Stone test 2024-03-27 11:08:26 +01:00
Martin Povišer 4570d064e5 techmap: Split out Kogge-Stone into a separate file 2024-03-27 11:07:24 +01:00
github-actions[bot] 0a854cf4ce Bump version 2024-03-26 00:15:18 +00:00
N. Engelhardt c98cdc2a42
Merge pull request #4184 from povik/check-loop-edges 
Use cell edges data in `check`, improve messages
 2024-03-25 16:19:35 +01:00
Miodrag Milanović c9d9b9ec2c
Merge pull request #4270 from YosysHQ/krys/config-none 
Change default CONFIG to none
 2024-03-25 16:13:32 +01:00
N. Engelhardt 6248d5901b
Merge pull request #4297 from chenrui333/fix-master-branch-refs 
chore: fix master branch refs
 2024-03-25 16:01:33 +01:00
Martin Povišer c38201e15d techmap: Add a Kogge-Stone option for `$lcu` mapping 2024-03-25 14:56:17 +01:00
Rui Chen b57a803f60
chore: fix master branch refs 
Signed-off-by: Rui Chen <rui@chenrui.dev>
 2024-03-24 00:41:54 -04:00
Peter Gadfort 160e3e089a add port statistics to stat command 2024-03-22 09:20:20 -04:00
Miodrag Milanovic 4367e176fb code split and cleanup 2024-03-19 09:15:04 +01:00
github-actions[bot] d73f71e813 Bump version 2024-03-19 00:20:31 +00:00
Krystine Sherwin c6795cefc5
docs: Install python requirements 2024-03-19 06:05:03 +13:00
Krystine Sherwin f72ddfb09d docs: Fix repo file links 2024-03-19 05:57:26 +13:00
Krystine Sherwin 29c8a3bef9 docs: Fix splice.v in verific 2024-03-19 05:57:26 +13:00
N. Engelhardt 3f54bf102c
Merge pull request #3907 from YosysHQ/krys/docs 
Manual rewrite and presentation merge
 2024-03-18 17:12:57 +01:00
Miodrag Milanovic 9eebc80170 handle standard types 2024-03-18 10:35:01 +01:00
Krystine Sherwin ff10aeebd6
Fix some synth_* help messages 
Mostly memory_libmap arg checks; puts the checks into an else block on the `if (help_mode)` check to avoid cases like `synth_ice40` listing `-no-auto-huge [-no-auto-huge]`.
Also fix `map_iopad` section being empty in `synth_fabulous`.
 2024-03-18 11:33:18 +13:00
Krystine Sherwin 3eeefd23e3
Typo fixup(s) 2024-03-18 11:09:23 +13:00
Krystine Sherwin 49f1bea1d2
docs: Add synth_ice40 to macro checks 2024-03-18 11:01:09 +13:00
Krystine Sherwin b6ffdec2ce
docs: Update OSS CAD suite info 2024-03-18 10:45:31 +13:00
Krystine Sherwin d2bf5a83af
Merge branch 'origin/master' into krys/docs 2024-03-18 10:39:30 +13:00
Krystine Sherwin 2832034877
docs: Clarify install instructions 
`config-clang` is the default, and doesn't need to be run first.  Previous instructions were ambiguous about that point.
Add note on using a different `CXX`.
 2024-03-18 10:35:01 +13:00
Krystine Sherwin bc9cccacf2
docs: Move fifo localparams into module def 
Fix for failing CI.
 2024-03-18 10:02:40 +13:00
github-actions[bot] 3231c1cd93 Bump version 2024-03-16 00:14:56 +00:00
N. Engelhardt 584692d53c
Merge pull request #4281 from YosysHQ/cat/issue-template-wasm 
Add WebAssembly as a platform to `ISSUE_TEMPLATE/bug_report.yml`
 2024-03-15 10:01:26 +01:00
Miodrag Milanovic 7c09fa572e real number handling and default to string 2024-03-14 10:37:56 +01:00
Miodrag Milanovic 4279cea33a improve handling VHDL constants 2024-03-14 10:37:56 +01:00
Miodrag Milanovic 858eae5572 verific_const: convert VHDL values to RTLIL consts 2024-03-14 10:37:56 +01:00
Catherine 29e3e10378
Add WebAssembly as a platform to ISSUE_TEMPLATE/bug_report.yml. 2024-03-13 10:04:13 +00:00
github-actions[bot] b3124f30e4 Bump version 2024-03-13 00:15:33 +00:00
Miodrag Milanovic 18cec2d9a9 Next dev cycle 2024-03-12 08:57:48 +01:00
Miodrag Milanovic 00338082b0 Release version 0.39 2024-03-12 08:55:10 +01:00
github-actions[bot] 0944664e60 Bump version 2024-03-12 00:15:21 +00:00
Krystine Sherwin 643c9540da
Makefile: reorder CONFIG=none check 2024-03-12 09:39:25 +13:00
Krystine Sherwin e0389436da
Makefile: Remove narrowing from ABCMKARGS 2024-03-12 09:18:38 +13:00
N. Engelhardt 0909c2ef5e
Merge pull request #4268 from jix/smtbmc-track-assumes 
smtbmc: Add --track-assumes and --minimize-assumes options
 2024-03-11 16:34:30 +01:00
Jannis Harder 42122e240e smtbmc: Add --track-assumes and --minimize-assumes options 
The --track-assumes option makes smtbmc keep track of which assumptions
were used by the solver when reaching an unsat case and to output that
set of assumptions. This is particularly useful to debug PREUNSAT
failures.

The --minimize-assumes option can be used in addition to --track-assumes
which will cause smtbmc to spend additional solving effort to produce a
minimal set of assumptions that are sufficient to cause the unsat
result.
 2024-03-11 15:13:11 +01:00
N. Engelhardt e4f11eb0a0
Merge pull request #4228 from povik/synth-inject 
synth: Introduce `-extra-map` for amending techmap
 2024-03-11 14:55:45 +01:00
Martin Povišer d42c04bc48
Merge pull request #4274 from YosysHQ/fix_warning 
fix compile warning
 2024-03-11 10:58:48 +01:00
Miodrag Milanovic 5e05300e7b fix compile warning 2024-03-11 10:55:09 +01:00
Martin Povišer 206d894c56 check: Omit private wires in loop report 2024-03-11 10:45:36 +01:00
Martin Povišer 5924d97381 tests: Remove part of test involving combinational loops 2024-03-11 10:45:36 +01:00
Martin Povišer d01728aaa5 celledges: Register async FF paths 2024-03-11 10:45:36 +01:00
Martin Povišer 87e72ef86f celledges: Add read ports arst paths 2024-03-11 10:45:17 +01:00
Martin Povišer 4a10e78777 celledges: Emit empty edges for write/init ports 2024-03-11 10:45:17 +01:00
Martin Povišer e4296072c4 check: Rephrase regex for portability 2024-03-11 10:45:17 +01:00
Martin Povišer 4fdcf388d3 check: Assert edges data is not out-of-bounds 2024-03-11 10:45:17 +01:00
Martin Povišer e1e77a7fa9 check: Extend testing 2024-03-11 10:45:17 +01:00