mirror of https://github.com/YosysHQ/yosys.git
improve handling VHDL constants
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858eae5572
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4279cea33a
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@ -223,7 +223,7 @@ RTLIL::IdString VerificImporter::new_verific_id(Verific::DesignObj *obj)
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//
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// Note: For signed values, verific uses <len>'sb<bits> and decimal values can
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// also be negative.
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static const RTLIL::Const verific_const(const char *value, bool from_vhdl, bool allow_string = true, bool output_signed = false)
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static const RTLIL::Const verific_const(const char *value, DesignObj *obj, bool allow_string = true, bool output_signed = false)
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{
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size_t found;
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char *end;
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@ -231,7 +231,7 @@ static const RTLIL::Const verific_const(const char *value, bool from_vhdl, bool
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bool is_signed = false;
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RTLIL::Const c;
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std::string val = std::string(value);
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if (from_vhdl) {
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if (obj->IsFromVhdl()) {
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if (val.size()>1 && val[0]=='\"' && val.back()=='\"') {
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std::string data = val.substr(1,val.size()-2);
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bool isBinary = std::all_of(data.begin(), data.end(), [](char c) {return c=='1' || c=='0'; });
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@ -245,6 +245,10 @@ static const RTLIL::Const verific_const(const char *value, bool from_vhdl, bool
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((decimal = std::strtol(value, &end, 10)), !end[0])) {
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is_signed = output_signed;
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c = RTLIL::Const((int)decimal, 32);
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} else if (val == "false") {
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c = RTLIL::Const::from_string("0");
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} else if (val == "true") {
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c = RTLIL::Const::from_string("1");
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} else {
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log_error("non-expected '%s' constant found", value);
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}
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@ -294,7 +298,7 @@ void VerificImporter::import_attributes(dict<RTLIL::IdString, RTLIL::Const> &att
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FOREACH_ATTRIBUTE(obj, mi, attr) {
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if (attr->Key()[0] == ' ' || attr->Value() == nullptr)
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continue;
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attributes[RTLIL::escape_id(attr->Key())] = verific_const(attr->Value(), obj->IsFromVhdl());
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attributes[RTLIL::escape_id(attr->Key())] = verific_const(attr->Value(), obj);
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}
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if (nl) {
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@ -316,7 +320,7 @@ void VerificImporter::import_attributes(dict<RTLIL::IdString, RTLIL::Const> &att
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const char *k, *v;
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FOREACH_MAP_ITEM(type_range->GetEnumIdMap(), mi, &k, &v) {
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if (nl->IsFromVerilog()) {
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auto const value = verific_const(v, nl->IsFromVhdl(), false);
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auto const value = verific_const(v, nl, false);
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attributes.emplace(stringf("\\enum_value_%s", value.as_string().c_str()), RTLIL::escape_id(k));
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}
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@ -1322,7 +1326,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
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MapIter mi;
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FOREACH_PARAMETER_OF_NETLIST(nl, mi, param_name, param_value) {
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module->avail_parameters(RTLIL::escape_id(param_name));
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module->parameter_default_values[RTLIL::escape_id(param_name)] = verific_const(param_value, nl->IsFromVhdl());
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module->parameter_default_values[RTLIL::escape_id(param_name)] = verific_const(param_value, nl);
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}
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SetIter si;
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@ -2022,7 +2026,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
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const char *param_value ;
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if (is_blackbox(inst->View())) {
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FOREACH_PARAMETER_OF_INST(inst, mi2, param_name, param_value) {
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cell->setParam(RTLIL::escape_id(param_name), verific_const(param_value, nl->IsFromVhdl()));
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cell->setParam(RTLIL::escape_id(param_name), verific_const(param_value, inst->View()));
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}
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}
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