mirror of https://github.com/YosysHQ/yosys.git
celledges: Emit empty edges for write/init ports
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@ -341,6 +341,18 @@ void memrd_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
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db->add_edge(cell, ID::ADDR, j, ID::DATA, k, -1);
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}
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void mem_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
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{
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if (cell->type == ID($mem_v2))
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packed_mem_op(db, cell);
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else if (cell->type.in(ID($memrd), ID($memrd_v2)))
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memrd_op(db, cell);
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else if (cell->type.in(ID($memwr), ID($memwr_v2), ID($meminit)))
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return; /* no edges here */
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else
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log_abort();
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}
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PRIVATE_NAMESPACE_END
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bool YOSYS_NAMESPACE_PREFIX AbstractCellEdgesDatabase::add_edges_from_cell(RTLIL::Cell *cell)
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@ -395,13 +407,8 @@ bool YOSYS_NAMESPACE_PREFIX AbstractCellEdgesDatabase::add_edges_from_cell(RTLIL
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return true;
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}
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if (cell->type == ID($mem_v2)) {
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packed_mem_op(this, cell);
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return true;
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}
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if (cell->type.in(ID($memrd), ID($memrd_v2))) {
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memrd_op(this, cell);
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if (cell->type.in(ID($mem_v2), ID($memrd), ID($memrd_v2), ID($memwr), ID($memwr_v2), ID($meminit))) {
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mem_op(this, cell);
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return true;
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}
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