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7333 Commits

Author SHA1 Message Date
Eddie Hung 076af2e617 Missing newline 2019-08-20 20:37:52 -07:00
Eddie Hung 4cc74346f1 Fix compile error 2019-08-20 20:27:05 -07:00
Eddie Hung 9b9d759451 Fix copy-paste typo 2019-08-20 20:18:51 -07:00
Eddie Hung b7a48e3e0f Merge remote-tracking branch 'origin/master' into xc7dsp 2019-08-20 20:18:17 -07:00
Eddie Hung 64d62710de Oops 2019-08-20 20:07:38 -07:00
Eddie Hung affe9c9c1a Merge branch 'eddie/fix_techmap' into xaig_arrival 2019-08-20 20:06:47 -07:00
Eddie Hung fe61dcce8b Grammar 2019-08-20 20:05:51 -07:00
Eddie Hung fce8dc7db2 Add test 2019-08-20 20:05:16 -07:00
Eddie Hung 193eae0c84 techmap -max_iter to apply to each module individually 2019-08-20 19:50:20 -07:00
Eddie Hung 57493e328a techmap -max_iter to apply to each module individually 2019-08-20 19:48:16 -07:00
Eddie Hung c26c556384 xilinx to use abc_map.v with -max_iter 1 2019-08-20 19:47:11 -07:00
Eddie Hung 6b1b03d9f7 ecp5: remove DPR16X4 from abc_unmap.v 2019-08-20 19:20:17 -07:00
Eddie Hung d46dc9c5b4 ecp5 to use -max_iter 1 2019-08-20 19:18:36 -07:00
Eddie Hung 55acf3120f ecp5 to use abc_map.v and _unmap.v 2019-08-20 18:59:03 -07:00
Eddie Hung 4cd1d21bfe Add (* abc_arrival=<int> *) doc 2019-08-20 18:27:16 -07:00
Eddie Hung 343039496b Add reference to FD* timing 2019-08-20 18:22:58 -07:00
Eddie Hung 091bf4a18b Remove sequential extension 2019-08-20 18:16:37 -07:00
Eddie Hung bbab608691 Remove SRL* delays from cells_sim.v 2019-08-20 18:14:40 -07:00
Eddie Hung fad15d276d retime_mode -> dff_mode 2019-08-20 18:08:58 -07:00
Eddie Hung aa2d3af631 LUTMUX -> LUTMUX6 2019-08-20 18:08:07 -07:00
Eddie Hung 30a379b5b6 Cleanup techmap in map_luts 2019-08-20 17:59:31 -07:00
Eddie Hung 3b52d6e29c Move `techmap abc_map.v` into map_luts 2019-08-20 17:55:12 -07:00
Eddie Hung 54284aaa98 Remove delays from abc_map.v 2019-08-20 17:52:27 -07:00
Eddie Hung 96f00e9147 Typo 2019-08-20 17:51:50 -07:00
Eddie Hung 8f666ebac1 Merge remote-tracking branch 'origin/master' into xaig_dff 2019-08-20 17:36:14 -07:00
Eddie Hung 1b5d2de1d4 Do not sigmap! 2019-08-20 15:23:26 -07:00
Eddie Hung 0ca397f087 Deprecate `abc_scc_break` attribute 2019-08-20 15:10:01 -07:00
Eddie Hung e273ed5275 Wrap SRL{16,32} too 2019-08-20 15:09:38 -07:00
Eddie Hung 808f07630f Wrap LUTRAMs in order to capture comb/seq behaviour 2019-08-20 14:49:11 -07:00
Eddie Hung c00d72cdb3 Minor refactor 2019-08-20 14:47:58 -07:00
Eddie Hung 0079e9b4a6 Add LUTRAM delays 2019-08-20 13:53:38 -07:00
Eddie Hung 505d062daf Fix use of {CLK,EN}_POLARITY, also add a FIXME 2019-08-20 13:33:31 -07:00
Eddie Hung 8d0cffaf20 Remove mapping rules 2019-08-20 13:11:39 -07:00
Eddie Hung 33960dd3d8
Merge pull request #1209 from YosysHQ/eddie/synth_xilinx 
[WIP] synth xilinx renaming, as per #1184
 2019-08-20 12:55:26 -07:00
Eddie Hung 5eda5fc7eb Remove -icells 2019-08-20 12:41:11 -07:00
Eddie Hung be9e4f1b67 Use abc_{map,unmap,model}.v 2019-08-20 12:39:11 -07:00
Eddie Hung c4d4c6db3f Merge remote-tracking branch 'origin/master' into xaig_dff 2019-08-20 12:00:12 -07:00
Eddie Hung 14c03861b6
Merge pull request #1304 from YosysHQ/eddie/abc9_refactor 
Refactor abc9 to use port attributes, not module attributes
 2019-08-20 11:59:31 -07:00
Eddie Hung d9fe4cccbf Merge remote-tracking branch 'origin/master' into eddie/synth_xilinx 2019-08-20 11:57:52 -07:00
SergeyDegtyar 71dd412ac5 Fix tests; Remove simulation; 
- Add -map and -assert options for equiv_opt;
	!!! '-assert' option was commented for the next tests (unproven
$equiv cells was found):
		- dffs;
		- div_mod;
		- latches;
		- mul_pow;
- Add design -load;
- Remove simulations;
 2019-08-20 15:52:25 +03:00
Clifford Wolf ba71e4f8f2
Merge pull request #1298 from YosysHQ/clifford/pmgen 
Improvements in pmgen
 2019-08-20 11:39:42 +02:00
Clifford Wolf d0117d7d12
Merge branch 'master' into clifford/pmgen 2019-08-20 11:39:23 +02:00
Clifford Wolf 6ffb910d12 Add test case for real parameters 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-20 11:38:21 +02:00
Clifford Wolf c25c1e742b
Merge pull request #1308 from jakobwenzel/real_params 
Handle real values when deriving ast modules
 2019-08-20 11:37:26 +02:00
SergeyDegtyar 153ec0541c Add new tests for ice40 architecture 2019-08-20 07:50:05 +03:00
whitequark 749ff864aa
Merge pull request #1309 from whitequark/proc_clean-fix-1268 
proc_clean: fix order of switch insertion
 2019-08-20 00:45:41 +00:00
Eddie Hung 1f03154a0c Merge remote-tracking branch 'origin/master' into xaig_dff 2019-08-19 15:19:32 -07:00
Eddie Hung 526e081342 Add arrival times for SRL outputs 2019-08-19 15:15:43 -07:00
Eddie Hung 45d4b33f0c Output i/o/h extensions even if no boxes or flops 2019-08-19 13:17:31 -07:00
Eddie Hung b71212ddea Add BRAM arrival times 2019-08-19 12:46:35 -07:00