riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
5,099 Commits 81 Branches 48 Tags 63 MiB
Commit Graph

5099 Commits

Author SHA1 Message Date
Eddie Hung adc6efb584 Recognise default entry in case even if all cases covered (#931) 2019-04-11 12:34:51 -07:00
Eddie Hung 233edf00fe Fix cells_map.v some more 2019-04-11 10:48:14 -07:00
Eddie Hung 8658b56a08 More fine tuning 2019-04-11 10:08:05 -07:00
Eddie Hung 0ec8564099 Fix cells_map.v 2019-04-11 10:04:58 -07:00
Eddie Hung bca3779657 Fix typo 2019-04-11 09:25:19 -07:00
Eddie Hung 87b8d29a90 Juggle opt calls in synth_xilinx 2019-04-11 09:13:39 -07:00
Eddie Hung 227cc54c16 Merge branch 'xaig' into xc7mux 2019-04-10 18:07:11 -07:00
Eddie Hung 2217d59e29 Add non-input bits driven by unrecognised cells as ci_bits 2019-04-10 18:06:33 -07:00
Eddie Hung cd7b2de27f WIP for cells_map.v -- maybe working? 2019-04-10 18:05:09 -07:00
Eddie Hung 3d577586fd Try splitting $shiftx with Y_WIDTH > 1 into Y_WIDTH = 1 2019-04-10 16:15:23 -07:00
Eddie Hung 3f5dab0d09 Fix for when B_SIGNED = 1 2019-04-10 14:51:10 -07:00
Eddie Hung 32561332b2 Update doc for synth_xilinx 2019-04-10 14:48:58 -07:00
Eddie Hung bf92218e0f Merge branch 'xaig' into xc7mux 2019-04-10 14:03:09 -07:00
Eddie Hung 1a49cf29d8 parse_aiger() to rename all $lut cells after "clean" 2019-04-10 14:02:23 -07:00
Eddie Hung 17a02df05c ff_map.v after abc 2019-04-10 12:36:06 -07:00
Eddie Hung 1ec949d5ed Tidy up 2019-04-10 09:02:42 -07:00
Eddie Hung 526aef9c2a Move map_cells to before map_luts 2019-04-10 08:50:31 -07:00
Eddie Hung e0b46eb4cb WIP for $shiftx to wide mux 2019-04-10 08:49:55 -07:00
Eddie Hung 4dac9818bd Update LUT delays 2019-04-10 08:49:39 -07:00
Eddie Hung 9a6da9a79a synth_* with -retime option now calls abc with -D 1 as well 2019-04-10 08:32:53 -07:00
Eddie Hung 5f4024ffd2 Revert "abc -dff now implies "-D 0" otherwise retiming doesn't happen" 
This reverts commit 19271bd996.
 2019-04-10 08:31:40 -07:00
Eddie Hung 78d35a86c0 Revert ""&nf -D 0" fails => use "-D 1" instead" 
This reverts commit 3c253818ca.
 2019-04-10 08:31:35 -07:00
Eddie Hung c89cd48f58 Merge remote-tracking branch 'origin/master' into eddie/fix_retime 2019-04-10 08:23:00 -07:00
Eddie Hung 3e368593eb Add cells.lut to techlibs/xilinx/ 2019-04-09 14:33:37 -07:00
Eddie Hung fd88ab5c83 synth_xilinx to call abc with -lut +/xilinx/cells.lut 2019-04-09 14:32:39 -07:00
Eddie Hung b9e19071b8 Add delays to cells.box 2019-04-09 14:32:10 -07:00
Eddie Hung d536379c62 Add "-lut <file>" support to abc9 2019-04-09 14:31:31 -07:00
Keith Rothman e107ccdde8 Fix LUT6_2 definition. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-04-09 11:43:19 -07:00
Eddie Hung f2042fc7c4 synth_xilinx with abc9 to use -box 2019-04-09 11:01:46 -07:00
Eddie Hung 2ae26b986c Add techlibs/xilinx/cells.box 2019-04-09 10:58:58 -07:00
Eddie Hung 7e304c362b Add "-box" option to abc9 2019-04-09 10:58:06 -07:00
Eddie Hung bd523abef5 Add 'setundef -zero' call prior to aigmap in abc9 2019-04-09 10:32:58 -07:00
Eddie Hung 3b6f85b0a6 Comment out 2019-04-09 10:09:43 -07:00
Eddie Hung 3fc474aa73 Add support for synth_xilinx -abc9 and ignore abc9 -dress opt 2019-04-09 10:06:44 -07:00
Zachary Snow 5855024ccc support repeat loops with constant repeat counts outside of constant functions 2019-04-09 12:28:32 -04:00
Keith Rothman 5e0339855f Add additional cells sim models for core 7-series primatives. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-04-09 09:01:53 -07:00
Eddie Hung 0deaccbaae
Fix a few typos 2019-04-08 16:46:33 -07:00
Eddie Hung 12c34136ba More space fixing 2019-04-08 16:40:17 -07:00
Eddie Hung 36efec01b8 Fix spacing 2019-04-08 16:37:22 -07:00
Eddie Hung bca3cf6843 Merge branch 'master' into xaig 2019-04-08 16:31:59 -07:00
Eddie Hung 6797f6b6c4 $_XILINX_SHREG_ to preserve src attribute 2019-04-08 16:24:20 -07:00
Eddie Hung f6c354c55b Update CHANGELOG 2019-04-08 16:22:07 -07:00
Eddie Hung 7e773741ab Merge branch 'undo_pr895' into xc7srl 2019-04-08 16:07:52 -07:00
Eddie Hung 13fc70d7a4 Undo #895 by instead setting an attribute 2019-04-08 16:05:24 -07:00
Eddie Hung 93b1621911 Cope with undoing #895 2019-04-08 15:57:07 -07:00
Clifford Wolf e194e65358
Merge pull request #919 from YosysHQ/multiport_transp 
memory_bram: Fix multiport make_transp
 2019-04-08 21:14:05 +02:00
Eddie Hung d3930ca79e Revert "Remove handling for $pmux, since #895" 
This reverts commit aa693d5723.
 2019-04-08 12:01:06 -07:00
David Shah 2bf3ca6443 memory_bram: Fix multiport make_transp 
Signed-off-by: David Shah <dave@ds0.me>
 2019-04-07 16:56:31 +01:00
Benedikt Tutzer e19981ab61 Suppress error from the compiler run during libboost-python* detection 2019-04-07 10:11:35 +02:00
Eddie Hung 1d526b7f06 Call shregmap twice -- once for variable, another for fixed 2019-04-05 17:35:49 -07:00