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148 Commits

Author SHA1 Message Date
Clifford Wolf 5c166e76e5 Added $initstate cell type and vlog function 2016-07-21 14:23:22 +02:00
Clifford Wolf d7763634b6 After reading the SV spec, using non-standard predict() instead of expect() 2016-07-21 13:34:33 +02:00
Clifford Wolf 721f1f5ecf Added basic support for $expect cells 2016-07-13 16:56:17 +02:00
Ruben Undheim 545bcb37e8 Allow defining input ports as "input logic" in SystemVerilog 2016-06-20 20:16:37 +02:00
Ruben Undheim 178ff3e7f6 Added support for SystemVerilog packages with localparam definitions 2016-06-18 10:53:55 +02:00
Clifford Wolf 060bf4819a Small improvements in Verilog front-end docs 2016-05-20 16:21:35 +02:00
Clifford Wolf 0bc95f1e04 Added "yosys -D" feature 2016-04-21 23:28:37 +02:00
Clifford Wolf 5a09fa4553 Fixed handling of parameters and const functions in casex/casez pattern 2016-04-21 15:31:54 +02:00
Clifford Wolf 33c10350b2 Fixed Verilog parser fix and more similar improvements 2016-03-15 12:22:31 +01:00
Andrew Becker 81d4e9e7c1 Use left-recursive rule for cell_port_list in Verilog parser. 2016-03-15 12:03:40 +01:00
Clifford Wolf 35a6ad4cc1 Fixed typos in verilog_defaults help message 2016-03-10 11:14:51 +01:00
Clifford Wolf 34f2b84fb6 Fixed handling of parameters and localparams in functions 2015-11-11 10:54:35 +01:00
Clifford Wolf 5308c1e02a Fixed bug in verilog parser 2015-10-15 15:19:23 +02:00
Clifford Wolf f13e387321 SystemVerilog also has assume(), added implicit -D FORMAL 2015-10-13 14:21:20 +02:00
Clifford Wolf ba4cce9f19 Added support for "parameter" and "localparam" in global context 2015-10-07 14:59:08 +02:00
Clifford Wolf e2e092b144 Added read_verilog -nodpi 2015-09-23 08:23:38 +02:00
Clifford Wolf b845b77f86 Fixed support for $write system task 2015-09-23 07:10:56 +02:00
Clifford Wolf a3a13cce32 Fixed detection of "task foo(bar);" syntax error 2015-09-22 21:34:21 +02:00
Clifford Wolf 4b8200eb49 Fixed segfault on invalid verilog constant 1'b_ 2015-09-22 08:13:09 +02:00
Clifford Wolf a7ab9172f9 Small corrections to const2ast warning messages 2015-08-17 16:22:53 +02:00
Florian Zeitz 0491042849 Check base-n literals only contain valid digits 2015-08-17 15:37:33 +02:00
Florian Zeitz 64ccbf8510 Warn on literals exceeding the specified bit width 2015-08-17 15:27:35 +02:00
Larry Doolittle 6c00704a5e Another block of spelling fixes 
Smaller this time
 2015-08-14 23:27:05 +02:00
Clifford Wolf 0350074819 Re-created command-reference-manual.tex, copied some doc fixes to online help 2015-08-14 11:27:19 +02:00
Clifford Wolf 84bf862f7c Spell check (by Larry Doolittle) 2015-08-14 10:56:05 +02:00
Clifford Wolf e4ef000b70 Adjust makefiles to work with out-of-tree builds 
This is based on work done by Larry Doolittle
 2015-08-12 15:04:44 +02:00
Clifford Wolf 45ee2ba3b8 Fixed handling of [a-fxz?] in decimal constants 2015-08-11 11:32:37 +02:00
Marcus Comstedt c836faae3e Add -noautowire option to verilog frontend 2015-08-01 12:16:54 +02:00
Clifford Wolf 6c84341f22 Fixed trailing whitespaces 2015-07-02 11:14:30 +02:00
Clifford Wolf 7ff802e199 Verilog front-end: define `BLACKBOX in -lib mode 2015-04-19 21:30:46 +02:00
Clifford Wolf a923a63a89 Ignore celldefine directive in verilog front-end 2015-03-25 19:46:12 +01:00
Clifford Wolf 1f1deda888 Added non-std verilog assume() statement 2015-02-26 18:47:39 +01:00
Clifford Wolf dc1a0f06fc Parser support for complex delay expressions 2015-02-20 10:21:36 +01:00
Clifford Wolf e0e6d130cd YosysJS stuff 2015-02-19 13:36:54 +01:00
Clifford Wolf 7f1a1759d7 Added "read_verilog -nomeminit" and "nomeminit" attribute 2015-02-14 11:21:12 +01:00
Clifford Wolf ef151b0b30 Fixed handling of "//" in filenames in verilog pre-processor 2015-02-14 08:41:03 +01:00
Clifford Wolf 4f68a77e3f Improved read_verilog support for empty behavioral statements 2015-02-10 12:17:29 +01:00
Clifford Wolf df9d096a7d Ignoring more system task and functions 2015-01-15 13:08:19 +01:00
Fabio Utzig fff6f00b3c Enable bison to be customized 2015-01-08 09:56:20 -02:00
Clifford Wolf 1bd67d792e Define YOSYS and SYNTHESIS in preproc 2015-01-02 17:11:54 +01:00
Clifford Wolf 7751c491fb Improved some warning messages 2014-12-27 03:40:27 +01:00
Clifford Wolf 1282a113da Fixed supply0/supply1 with many wires 2014-12-11 13:56:20 +01:00
Clifford Wolf 76c83283c4 Fixed minor bug in parsing delays 2014-11-24 14:48:07 +01:00
Clifford Wolf 56c7d1e266 Fixed two minor bugs in constant parsing 2014-11-24 14:39:24 +01:00
Clifford Wolf 87333f3ae2 Added warning for use of 'z' constants in HDL 2014-11-14 19:59:50 +01:00
Clifford Wolf 4e5350b409 Fixed parsing of nested verilog concatenation and replicate 2014-11-12 19:10:35 +01:00
Clifford Wolf fe829bdbdc Added log_warning() API 2014-11-09 10:44:23 +01:00
Clifford Wolf a21481b338 Fixed parsing of "module mymod #( parameter foo = 1, bar = 2 ..." 2014-10-30 14:01:02 +01:00
Clifford Wolf f9c096eeda Added support for task and function args in parentheses 2014-10-27 13:21:57 +01:00
Clifford Wolf c5eb5e56b8 Re-introduced Yosys::readsome() helper function 
(f.read() + f.gcount() made problems with lines > 16kB)
 2014-10-23 10:58:36 +02:00