Marcelina Kościelnicka
f965b3fa54
rtlil: Disallow 0-width chunks in SigSpec.
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Among other problems, this also fixes equality comparisons between
SigSpec by enforcing a canonical form.
Also fix another minor issue with possible non-canonical SigSpec.
Fixes #2623 .
2021-03-15 17:16:24 +01:00
whitequark
e178d0367a
Merge pull request #2658 from zachjs/parameters-across-files
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sv: allow globals in one file to depend on globals in another
2021-03-14 15:02:16 +00:00
Zachary Snow
640b9927fa
sv: allow globals in one file to depend on globals in another
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This defers the simplification of globals so that globals in one file
may depend on globals in other files. Adds a simplify() call downstream
because globals are appended at the end.
2021-03-12 11:22:41 -05:00
whitequark
396ad17e06
Merge pull request #2653 from zachjs/global-parameter
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verilog: disallow overriding global parameters
2021-03-12 01:34:06 +00:00
whitequark
feff32914b
Merge pull request #2642 from whitequark/cxxrtl-noproc-fixes
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CXXRTL: some -noproc fixes
2021-03-11 20:01:10 +00:00
Zachary Snow
cb9f3b6abf
verilog: disallow overriding global parameters
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It was previously possible to override global parameters on a
per-instance basis. This could be dangerous when using positional
parameter bindings, hiding oversupplied parameters.
2021-03-11 12:36:51 -05:00
Miodrag Milanovic
81c2b92bb4
Add _pm.h files to GENLIST, fixes vcxsrc target
2021-03-11 15:56:32 +01:00
Dan Ravensloft
83fc5cc28b
Replace assert in xaiger with more useful error message
2021-03-10 22:35:06 +01:00
whitequark
26e01a67db
Merge pull request #2643 from zachjs/fix-param-no-default-log
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Fix param without default log line
2021-03-08 16:36:03 -08:00
Marcelina Kościelnicka
0b0e219765
Bump version
2021-03-08 20:18:11 +01:00
Marcelina Kościelnicka
a3528649c8
memory_dff: Remove now-useless write port handling.
2021-03-08 20:16:29 +01:00
Marcelina Kościelnicka
89c74ffd71
verilog: Use proc memory writes in the frontend.
2021-03-08 20:16:29 +01:00
Marcelina Kościelnicka
4e03865d5b
Add support for memory writes in processes.
2021-03-08 20:16:29 +01:00
Marcelina Kościelnicka
c00a29296c
sim: Avoid a crash on empty cell connection.
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Fixes #2513 .
2021-03-08 17:03:31 +01:00
Marcelina Kościelnicka
760284033d
proc_dff: Fix emitted FF when a register is not assigned in async reset
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Fixes #2619 .
2021-03-08 17:01:43 +01:00
Marcelina Kościelnicka
bc717abad2
memory_dff: Remove code looking for $mux cells.
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This job is now performed by `opt_dff`, which runs before this pass.
2021-03-08 16:58:12 +01:00
Marcelina Kościelnicka
d555454969
tests/bram: Do not generate write address collisions.
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These have no defined semantics, making the tests non-deterministic.
2021-03-08 16:53:03 +01:00
Zachary Snow
bdc4fd0e92
Fix param without default log line
2021-03-07 16:06:25 -05:00
Dan Ravensloft
9cdc6b5f2e
Replace assert in abc9_ops with more useful error message
2021-03-07 18:52:14 +01:00
whitequark
ab76d9cec5
cxxrtl: don't assert on edge sync rules tied to a constant.
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These are commonly the result of tying an async reset to an inactive
level.
2021-03-07 14:29:30 +00:00
whitequark
d1de08e38a
cxxrtl: allow `always` sync rules in debug_eval.
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These can be produced from `always @*` processes, if `-noproc`
is used.
2021-03-07 14:28:45 +00:00
whitequark
9bb839c613
Merge pull request #2626 from zachjs/param-no-default
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sv: support for parameters without default values
2021-03-07 05:48:03 -08:00
whitequark
72ae15c77c
Merge pull request #2632 from zachjs/width-limit
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verilog: impose limit on maximum expression width
2021-03-07 03:45:41 -08:00
Zachary Snow
b1a8e73a60
sv: fix some edge cases for unbased unsized literals
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- Fix explicit size cast of unbased unsized literals
- Fix unbased unsized literal bound directly to port
- Output `is_unsized` flag in `dumpAst`
2021-03-06 15:20:34 -05:00
Marcelina Kościelnicka
d245e2bae5
proc_clean: Fix empty case removal conditions.
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Fixes #2639 .
2021-03-06 17:39:50 +01:00
Marcelina Kościelnicka
3d2aef0bde
Remove a few functions that, in fact, did not exist in the first place.
2021-03-06 01:19:49 +01:00
Dan Ravensloft
55e5bd4213
Replace assert in addModule with more useful error message
2021-03-06 00:10:28 +01:00
whitequark
9dd813374e
Merge pull request #2635 from whitequark/cxxrtl-memrd-async-addr
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cxxrtl: follow aliases to outlines when emitting $memrd.ADDR
2021-03-05 05:30:19 -08:00
whitequark
06da2e0f18
Merge pull request #2634 from whitequark/cxxrtl-debug-wire-types
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cxxrtl: add pass debug flag to show assigned wire types
2021-03-05 04:57:22 -08:00
whitequark
b117f9bba8
Merge pull request #2633 from whitequark/cxxrtl-no-top
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cxxrtl: don't crash on empty designs
2021-03-05 04:14:07 -08:00
whitequark
14ce8bdaa6
cxxrtl: follow aliases to outlines when emitting $memrd.ADDR.
2021-03-05 12:09:02 +00:00
whitequark
8471808834
cxxrtl: add pass debug flag to show assigned wire types.
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Refs #2543 .
2021-03-05 11:58:59 +00:00
whitequark
a9a873a1d2
cxxrtl: don't crash on empty designs.
2021-03-05 11:05:19 +00:00
Zachary Snow
c18ddbcd82
verilog: impose limit on maximum expression width
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Designs with unreasonably wide expressions would previously get stuck
allocating memory forever.
2021-03-04 15:20:52 -05:00
Claire Xen
7d2097b005
Update command-reference-manual.tex
2021-03-04 16:45:21 +01:00
Claire Xen
6c56c083f8
Update README
2021-03-04 16:43:30 +01:00
Noah Moroze
90b40aa51f
clk2fflogic: nice names for autogenerated signals
2021-03-02 18:28:56 -05:00
Zachary Snow
d738b2c127
sv: support for parameters without default values
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- Modules with a parameter without a default value will be automatically
deferred until the hierarchy pass
- Allows for parameters without defaults as module items, rather than
just int the `parameter_port_list`, despite being forbidden in the LRM
- Check for parameters without defaults that haven't been overriden
- Add location info to parameter/localparam declarations
2021-03-02 10:43:53 -05:00
whitequark
375af199ef
Merge pull request #2620 from zachjs/port-int-types
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verilog: fix sizing of ports with int types in module headers
2021-03-01 22:46:07 -08:00
Zachary Snow
10a6bc9b81
verilog: fix sizing of ports with int types in module headers
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Declaring the ports as standard module items already worked as expected.
This adds a missing usage of `checkRange()` so that headers such as
`module m(output integer x);` now work correctly.
2021-03-01 13:39:05 -05:00
Marcelina Kościelnicka
0e0f84299a
Bump version
2021-03-01 19:33:05 +01:00
Zachary Snow
1ec5994100
verilog: fix handling of nested ifdef directives
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- track depth so we know whether to consider higher-level elsifs
- error on unmatched endif/elsif/else
2021-03-01 12:28:33 -05:00
Zachary Snow
b6904a8e53
Set aside extraneous tests in simple_abc9 test suite
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New test cases on one branch may be automatically copied from simple/ to
simple_abc9/, causing failures when switching to another branch. This
updates the simple_abc9 script to set aside extraneous tests in a
non-destructive way.
2021-03-01 12:13:11 -05:00
Claire Xen
004b780b8a
Merge pull request #2523 from tomverbeure/define_synthesis
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Add -nosynthesis flag for read_verilog command
2021-03-01 18:00:48 +01:00
Claire Xen
527c681a2b
Merge pull request #2524 from bkbncn/patch-1
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Add boost-python3
2021-03-01 17:46:33 +01:00
whitequark
7b47dd0f88
Merge pull request #2617 from RobertBaruch/doc
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RTLIL Documentation: switch in process is optional
2021-03-01 08:10:32 -08:00
whitequark
ca5f5ffcd6
Merge pull request #2615 from zachjs/genrtlil-conflict
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genrtlil: improve name conflict error messaging
2021-03-01 08:10:19 -08:00
whitequark
0fb4224ebc
Merge pull request #2618 from zachjs/int-types
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sv: extended support for integer types
2021-02-28 20:29:44 -08:00
Zachary Snow
0f5b646ab8
sv: extended support for integer types
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- Standard data declarations can now use any integer type
- Parameters and localparams can now use any integer type
- Function returns types can now use any integer type
- Fix `parameter logic`, `localparam reg`, etc. to be 1 bit (previously 32 bits)
- Added longint type (64 bits)
- Unified parser source for integer type widths
2021-02-28 16:31:56 -05:00
Robert Baruch
ca4b1afcb6
RTLIL Documentation: switch in process is optional
2021-02-27 09:58:03 -08:00