Merge pull request #2653 from zachjs/global-parameter

verilog: disallow overriding global parameters
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whitequark 2021-03-12 01:34:06 +00:00 committed by GitHub
commit 396ad17e06
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2 changed files with 18 additions and 0 deletions

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@ -1286,6 +1286,8 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump
}
else {
// must be global definition
if ((*it)->type == AST_PARAMETER)
(*it)->type = AST_LOCALPARAM; // cannot be overridden
(*it)->simplify(false, false, false, 1, -1, false, false); //process enum/other declarations
design->verilog_globals.push_back((*it)->clone());
current_scope.clear();

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@ -0,0 +1,16 @@
read_verilog -sv <<EOF
parameter P = 1;
module example(
output integer out
);
assign out = P;
endmodule
module top(
output integer out
);
example #(2) e1(out);
endmodule
EOF
logger -expect error "Can't find object for defparam" 1
hierarchy