Commit Graph

11435 Commits

Author SHA1 Message Date
Marcelina Kościelnicka a6081b46ce connect: Add -assert option, fix non-working sigmap.
Should be useful for writing tests.
2021-05-08 15:49:41 +02:00
Marcelina Kościelnicka 5c1e6a0e20 opt_dff: Fix NOT gates wired in reverse. 2021-05-04 21:03:40 +02:00
Miodrag Milanović d061b0e41a
Merge pull request #2738 from mdko/xilinx-blif
Fix use of blif name in synth_xilinx command
2021-04-27 11:46:41 +02:00
Michael Christensen 67d6f3973b Fix use of blif name in synth_xilinx command 2021-04-27 02:29:52 -07:00
Claire Xen 86a6ac7623
Merge pull request #2737 from YosysHQ/claire/fix2736
Remove duplicates from conns array in JSON front-end, fixes #2736
2021-04-26 17:54:30 +02:00
Claire Xenia Wolf 58290c0c77 Remove duplicates from conns array in JSON front-end, fixes #2736 2021-04-26 16:32:12 +02:00
Claire Xen a5adb00774
Merge pull request #2669 from YosysHQ/claire/ice40defaults
Add input default assignments to iCE40 cell library
2021-04-21 12:24:07 +02:00
Claire Xenia Wolf 46d3f03d27 Add default assignments to other SB_* simulation models
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2021-04-20 18:52:36 +02:00
Claire Xenia Wolf 8aee80040d Add default assignments to SB_LUT4
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2021-04-20 12:46:21 +02:00
Lofty dce037a62c quicklogic: ABC9 synthesis 2021-04-17 20:54:58 +02:00
Stefan Riesenberger a58571d0fe sf2: fix name of AND modules 2021-04-09 16:46:05 +02:00
whitequark 0b05452cf7
Merge pull request #2724 from whitequark/flatten-rewrite-memwr-memid
flatten: rewrite memid in memwr actions
2021-04-09 14:22:36 +00:00
whitequark c5c57e3f5e flatten: rewrite memid in memwr actions. 2021-04-09 09:46:53 +00:00
Zachary Snow 0ccc7229c0 preproc: test coverage for #2712 2021-03-30 12:23:18 -04:00
Marcelina Kościelnicka b7ea71e6e3 equiv: Suggest running async2sync or clk2fflogic where appropriate.
See #2713.
2021-03-30 18:20:21 +02:00
Zachary Snow ba2ff1ea98 verilog: revise hot comment warnings 2021-03-30 09:21:18 -04:00
Eddie Hung 8c5f379435
abc9: uniquify blackboxes like whiteboxes (#2695)
* abc9_ops: uniquify blackboxes too

* abc9_ops: update comment

* abc9_ops: allow bypass for param-less blackboxes

* Add tests
2021-03-29 22:02:06 -07:00
Eddie Hung 55dc5a4e4f
abc9: fix SCC issues (#2694)
* xilinx: add SCC test for DSP48E1

* xilinx: Gate DSP48E1 being a whitebox behind ALLOW_WHITEBOX_DSP48E1

Have a test that checks it works through ABC9 when enabled

* abc9 to break SCCs using $__ABC9_SCC_BREAKER module

* Add test

* abc9_ops: remove refs to (* abc9_keep *) on wires

* abc9_ops: do not bypass cells in an SCC

* Add myself to CODEOWNERS for abc9*

* Fix compile

* abc9_ops: run -prep_hier before scc

* Fix tests

* Remove bug reference pending fix

* abc9: fix for -prep_hier -dff

* xaiger: restore PI handling

* abc9_ops: -prep_xaiger sigmap

* abc9_ops: -mark_scc -> -break_scc

* abc9: eliminate hard-coded abc9.box from tests

Also tidy up

* Address review
2021-03-29 22:01:57 -07:00
Marcelina Kościelnicka 687f381b69 Bump version 2021-03-30 02:30:17 +02:00
Marcelina Kościelnicka 0505c604e7 preproc: Fix up conditional handling.
Fixes #2710.
Fixes #2711.
2021-03-30 02:29:26 +02:00
Zachary Snow 1af994802e gha: trim macOS dependencies
- Only install needed dependencies rather than using Brewfile
- Remove brew update (recent enough formulae already baked in)
- Saves ~16 minutes in macOS CI
2021-03-28 23:37:56 -04:00
Zachary Snow e314a05e0a gha: combine jobs using matrix 2021-03-28 18:29:29 -04:00
Zachary Snow d6d5c2ef34 rtlil: add const accessors for modules, wires, and cells 2021-03-25 10:44:08 -04:00
whitequark 4762ed90ff
Merge pull request #2702 from modwizcode/patch-1
Clarify bugpoint documentation regarding output
2021-03-24 23:39:19 +00:00
Iris Johnson 4c39189b13
Clarify bugpoint documentation regarding output
Bugpoint's current documentation does specify that the result of a run is stored as the current design,
however it's easy to skim over what that means in practice. 

Add a documentation comment to explain specifically that an after bugpoint `write_xyz` pass is required to save
the reduced design.
2021-03-24 16:24:33 -05:00
Zachary Snow c58bb1d2e1 ast: make design available to process_module() 2021-03-24 10:21:00 -04:00
Marcelina Kościelnicka 192601385f rtlil: Fix process memwr roundtrip.
Fixes #2646 fallout.
2021-03-23 19:49:47 +01:00
N. Engelhardt 049e3abf9b
Merge pull request #2696 from nakengelhardt/guidelines
split CodingReadme into multiple files
2021-03-23 17:41:13 +01:00
Marcelina Kościelnicka 4a35f244aa quicklogic: Add .gitignore file for test outputs. 2021-03-23 17:35:00 +01:00
Marcelina Kościelnicka 6b2100bf01 json: Improve the "processes in module" message a bit. 2021-03-23 15:53:49 +01:00
N. Engelhardt d9ec35a526 split CodingReadme into multiple files 2021-03-22 19:16:25 +01:00
Xiretza 92d5550a90 verilog: check entire user type stack for type definition 2021-03-21 19:35:13 -04:00
Zachary Snow 4f4e70876f sv: allow typenames as function return types 2021-03-19 12:08:43 -04:00
Miodrag Milanović 6a0d1e117d
Merge pull request #2681 from msinger/fix-issue2606
Fix check for bad std::regex
2021-03-19 08:47:07 +01:00
Xiretza 0c66141ed2 verilog: rebuild user_type_stack from globals before parsing file
This was actually a ticking UB bomb: after running the parser, the type
maps contain pointers to children of the current AST, which is
recursively deleted after the pass has executed. This leaves the
pointers in user_type_stack dangling, which just happened to never be a
problem due to another bug that causes typedefs from higher-level type
maps to never be considered.

Rebuilding the type stack from the design's globals ensures the AstNode
pointers are valid.
2021-03-18 20:52:36 -04:00
Marcelina Kościelnicka 3a12617ec0 Add simple CI using github actions. 2021-03-18 22:27:45 +01:00
Xiretza 3aa10e90ba modtools: fix use-after-free of cell pointers in ModWalker
cell_inputs and cell_outputs retain cell pointers as their keys across
invocations of setup(), which may however be invalidated in the meantime
(as happens in e.g. passes/opt/share.cc:1432). A later rehash of the
dicts (caused by inserting in ModWalker::add_wire()) will cause them to
be dereferenced.
2021-03-18 13:50:13 +01:00
Lofty f4298b057a quicklogic: PolarPro 3 support
Co-authored-by: Grzegorz Latosiński <glatosinski@antmicro.com>
Co-authored-by: Maciej Kurc <mkurc@antmicro.com>
Co-authored-by: Tarachand Pagarani <tpagarani@quicklogic.com>
Co-authored-by: Lalit Sharma <lsharma@quicklogic.com>
Co-authored-by: kkumar23 <kkumar@quicklogic.com>
2021-03-18 13:28:16 +01:00
Marcelina Kościelnicka 8740fdf1d7 ast: Use better parameter serialization for paramod names.
Calling log_signal is problematic for several reasons:

- with recent changes, empty string is serialized as { }, which violates
  the "no spaces in IdString" rule
- the type (plain / real / signed / string) is dropped, wrongly conflating
  functionally different values and potentially introducing a subtle
  elaboration bug

Instead, use a custom simple serialization scheme.
2021-03-18 00:52:00 +01:00
Michael Singer d05d47cc04 Fix check for bad std::regex (fixes #2606) 2021-03-17 23:35:26 +01:00
gatecat cae905f551 Blackbox all whiteboxes after synthesis
This prevents issues like processes in whiteboxes triggering an error in
the JSON backend.

Signed-off-by: gatecat <gatecat@ds0.me>
2021-03-17 21:07:20 +00:00
Zachary Snow c8b45a4a82 bugpoint: add runner option 2021-03-17 15:54:00 -04:00
Zachary Snow f71c2dcca6 sv: carry over global typedefs from previous files
This breaks the ability to use a global typename as a standard
identifier in a subsequent input file. This is otherwise backwards
compatible, including for sources which previously included conflicting
typedefs in each input file.
2021-03-17 15:53:52 -04:00
Xiretza 092e923330 verilog: fix buf/not primitives with multiple outputs
From IEEE1364-2005, section 7.3 buf and not gates:

> These two logic gates shall have one input and one or more outputs.
> The last terminal in the terminal list shall connect to the input of the
> logic gate, and the other terminals shall connect to the outputs of
> the logic gate.

yosys does not follow this and instead interprets the first argument as
the output, the second as the input and ignores the rest.
2021-03-17 11:44:03 -04:00
gatecat dd6d34f461 blackbox: Include whiteboxed modules
Signed-off-by: gatecat <gatecat@ds0.me>
2021-03-17 13:58:04 +00:00
Lofty 937392ad33 Replace assert in get_reference with more useful error message 2021-03-17 09:32:13 +01:00
Zachary Snow 4f187d53c5 verilog: support module scope identifiers in parametric modules 2021-03-16 11:01:30 -04:00
Marcelina Kościelnicka 3d9698153f json: Add support for memories.
Previously, memories were silently discarded by the JSON backend, making
round-tripping modules with them crash.

Since there are already some users using JSON to implement custom
external passes that use memories (and infer width/size from memory
ports), let's fix this by just making JSON backend and frontend support
memories as first-class objects.

Processes are still not supported, and will now cause a hard error.

Fixes #1908.
2021-03-15 17:19:19 +01:00
Marcelina Kościelnicka a55bf6375b proc_arst: Add special-casing of clock signal in conditionals.
The already-existing special case for conditionals on clock has been
remade as follows:

- now triggered for the last remaining edge trigger after all others
  have been converted to async reset, not just when there is only one
  sync rule in the first place
- does not require all contained assignments to be constant, as opposed
  to a reset conditional — merely const-folds the condition

In addition, the code has been refactored a bit; as a bonus, the
priority order of async resets found is now preserved in resulting sync
rule ordering (though this is not yet respected by proc_dff).

Fixes #2656.
2021-03-15 17:17:29 +01:00
Marcelina Kościelnicka 3af871f969 opt_clean: Remove init attribute bits together with removed DFFs.
Fixes #2546.
2021-03-15 17:16:53 +01:00