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sf2: fix name of AND modules

This commit is contained in:
Stefan Riesenberger 2021-04-09 15:44:08 +02:00 committed by Marcelina Kościelnicka
parent 0b05452cf7
commit a58571d0fe
1 changed files with 3 additions and 3 deletions
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6
techlibs/sf2/cells_sim.v
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@ -1,20 +1,20 @@
// https://coredocs.s3.amazonaws.com/Libero/12_0_0/Tool/sf2_mlg.pdf
module ADD2 (
module AND2 (
input A, B,
output Y
);
assign Y = A & B;
endmodule
module ADD3 (
module AND3 (
input A, B, C,
output Y
);
assign Y = A & B & C;
endmodule
module ADD4 (
module AND4 (
input A, B, C, D,
output Y
);