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5095 Commits

Author SHA1 Message Date
Eddie Hung 0364a5d811 Merge branch 'eddie/fix_retime' into xc7srl 2019-04-05 15:46:18 -07:00
Eddie Hung 9758701574 Move techamp t:$_DFF_?N? to before abc call 2019-04-05 15:39:05 -07:00
Eddie Hung 23a6533e98 Retry 2019-04-05 15:31:54 -07:00
Eddie Hung 3c253818ca "&nf -D 0" fails => use "-D 1" instead 2019-04-05 15:30:19 -07:00
Eddie Hung 8b6085254a Resolve @daveshah1 comment, update synth_xilinx help 2019-04-05 15:15:13 -07:00
Eddie Hung ff0912c75e synth_xilinx to techmap FFs after abc call, otherwise -retime fails 2019-04-05 14:43:06 -07:00
Eddie Hung 19271bd996 abc -dff now implies "-D 0" otherwise retiming doesn't happen 2019-04-05 14:42:25 -07:00
Eddie Hung 544843da71 techmap inside map_cells stage 2019-04-05 12:55:52 -07:00
Clifford Wolf dfb242c905 Add "read_ilang -lib" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-05 17:31:49 +02:00
Benedikt Tutzer cc270ea81b Autodetect Python paths and boost python libraries for different distributions 2019-04-05 11:56:01 +02:00
Clifford Wolf 75ca06526a Added missing argument checking to "mutate" command 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-04 18:10:10 +02:00
Eddie Hung 7b7ddbdba7 Merge branch 'map_cells_before_map_luts' into xc7srl 2019-04-04 08:13:34 -07:00
Eddie Hung e3f20b17af Missing techmap entry in help 2019-04-04 08:13:10 -07:00
Eddie Hung 2fb02247a7 Use soft-logic, not LUT3 instantiation 2019-04-04 08:10:40 -07:00
Eddie Hung 572603409c Merge branch 'map_cells_before_map_luts' into xc7srl 2019-04-04 07:54:42 -07:00
Eddie Hung d9cb787391 synth_xilinx to map_cells before map_luts 2019-04-04 07:48:13 -07:00
Eddie Hung 77755b5a66 Cleanup comments 2019-04-04 07:41:40 -07:00
Eddie Hung 736e19f02d t:$dff* -> t:$dff t:$dffe 2019-04-04 07:39:19 -07:00
Benedikt Tutzer cae657cebd Used PyImport_ImportModule instead of PyImport_Import to avoid the explicit conversion to a python string 2019-04-04 10:35:01 +02:00
Benedikt Tutzer 574dfb2ef9 Removed link to experimental filesystem library 2019-04-04 09:51:14 +02:00
Benedikt Tutzer e64b3f1074 Changed filesystem dependency to boost instead of experimental std library 2019-04-04 09:24:50 +02:00
Eddie Hung aa693d5723 Remove handling for $pmux, since #895 2019-04-03 08:35:32 -07:00
Eddie Hung 0e2d929cea -nosrl meant when -nobram 2019-04-03 08:28:07 -07:00
Eddie Hung ff385a5ad0 Remove duplicate STARTUPE2 2019-04-03 08:14:09 -07:00
Benedikt Tutzer c3486c4270 Removed compiler flags that are clang specific 2019-04-03 16:19:47 +02:00
Eddie Hung 88630cd02c Disable shregmap in synth_xilinx if -retime 2019-04-03 07:14:20 -07:00
Eddie Hung f7a0434d54 Add changelog entry 2019-04-03 07:05:28 -07:00
Benedikt Tutzer d330f4e009 Even less options for the preprocessor 2019-04-03 15:34:31 +02:00
Eddie Hung ef84b434a5
Merge pull request #913 from smunaut/fix_proc_mux 
proc_mux: Fix crash when trying to optimize non-existant mux to shiftx
 2019-04-03 06:27:41 -07:00
Benedikt Tutzer c5a8dceff8 Preprocessing does not need all the flags 2019-04-03 15:13:58 +02:00
Sylvain Munaut 39380c45ba proc_mux: Fix crash when trying to optimize non-existant mux to shiftx 
last_mux_cell can be NULL ...

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2019-04-03 14:50:12 +02:00
Benedikt Tutzer 827a96d3a3 Global lists in rtlil.cc are now static objects 2019-04-03 14:27:39 +02:00
Benedikt Tutzer fd7fb1377d Added cross-platform support for plugin-paths 2019-04-03 13:21:40 +02:00
Eddie Hung d8465590ac Merge remote-tracking branch 'origin/master' into xc7srl 2019-04-03 03:36:11 -07:00
Benedikt Tutzer bbfb43006d Improved Error reporting when Python passes are loaded 2019-04-03 12:21:56 +02:00
Benedikt Tutzer 0774a500d4 Added support for changing Yosys namespace 2019-04-03 12:21:21 +02:00
Benedikt Tutzer 539a7f3fbc Added cell_stats example 2019-04-03 11:24:50 +02:00
Benedikt Tutzer d287596be3 Added dependencies to README and travis configuration 2019-04-03 11:18:34 +02:00
Benedikt Tutzer adfd8d463d Autodetect highest installed python version 2019-04-03 11:17:50 +02:00
Clifford Wolf 721fa1cbd8
Merge pull request #912 from YosysHQ/bram_addr_en 
memory_bram: Consider read enable for address expansion register
 2019-04-03 10:00:18 +02:00
Clifford Wolf 3f6554d698
Merge pull request #910 from ucb-bar/memupdates 
Refine memory support to deal with general Verilog memory definitions.
 2019-04-03 09:59:11 +02:00
David Shah 6acbc016f4 memory_bram: Consider read enable for address expansion register 
Signed-off-by: David Shah <dave@ds0.me>
 2019-04-02 19:47:50 +01:00
Miodrag Milanovic df92e9bdc2 Make nobram false by default for gowin 2019-04-02 19:21:01 +02:00
Eddie Hung aaa2690a56
Merge pull request #895 from YosysHQ/pmux2shiftx 
RFC: Add a pmux-to-shiftx optimisation to proc_mux
 2019-04-02 00:16:14 -07:00
Jim Lawson 73b87e7807 Refine memory support to deal with general Verilog memory definitions. 2019-04-01 15:02:12 -07:00
Benedikt Tutzer 2586e09118 Removed generation of commented-out code 2019-04-01 15:05:30 +02:00
Benedikt Tutzer 7472c52686 Use addition assignment operator 2019-04-01 13:39:38 +02:00
Benedikt Tutzer 072c939380 Fixed identation 2019-04-01 13:36:01 +02:00
Clifford Wolf 22035c20ff
Merge pull request #907 from YosysHQ/clifford/fix906 
Build Verilog parser with -DYYMAXDEPTH=100000
 2019-03-30 00:09:42 +01:00
Clifford Wolf 584d2030bf Build Verilog parser with -DYYMAXDEPTH=100000, fixes #906 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-29 16:32:44 +01:00