mirror of https://github.com/YosysHQ/yosys.git
Added cell_stats example
This commit is contained in:
Benedikt Tutzer
parent
d287596be3
commit
539a7f3fbc
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@ -1,472 +0,0 @@
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from libyosys import *
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from scipy.sparse import coo_matrix
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from numpy import savetxt
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from enum import Enum
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class NodeType(Enum):
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GRAPH_CELL = 0
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GRAPH_PI = 1
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GRAPH_PO = 2
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GRAPH_CONST = 3
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GRAPH_WIRE = 4
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class NetlistElement:
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def __init__(self, design, module, name):
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self.design = design
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self.module = module
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self.name = name
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class Bit(NetlistElement):
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def __init__(self, bit, design, module, node, port, pos):
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super().__init__(design, module, IdString("\\__BIT__"))
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self.bit = bit
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self.node = node
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self.port = port
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self.pos = pos
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class Port(NetlistElement):
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def __init__(self, name):
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super().__init__(None, None, name)
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self.input = False
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self.output = False
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self.bits = []
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class Node(NetlistElement):
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def __init__(self, design, module, name, nodeType):
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super().__init__(design, module, name)
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self.nodeType = nodeType
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self.ports = []
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def __lt__(self, other):
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if isinstance(other, self.__class):
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if self.type == other.type:
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return self.name.str() < other.name.str()
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return self.type < other.type
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return False
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class PyCell(Node):
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def __init__(self, design, module, name, cell):
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super().__init__(design, module, name, NodeType.GRAPH_CELL)
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self.cell = cell
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class PyWire(Node):
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def __init__(self, design, module, name):
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super().__init__(design, module, name, NodeType.GRAPH_WIRE)
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class NetlistGraph:
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def __init__(self, design, module = None):
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self.design = design
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if module != None:
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self.module = module
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else:
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self.module = list(design.modules_.values())[0]
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self.cells = []
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self.wires = []
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self.nodes = []
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self.node_bits = []
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self.wire_bits = []
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self.node_index = {}
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self.node_bit_index = {}
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self.wire_bit_index = {}
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self.incoming = None
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self.outgoing = None
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self.create()
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def create(self):
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log_header(self.design, "Creating abstract graph representation of "
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+ "module " + self.module.name.str() + "\n")
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log_push()
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sigmap = SigMap(self.module)
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log(" Creating const node\n")
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const_node = Node(self.design, self.module, IdString("\\__CONST__"), NodeType.GRAPH_CONST)
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const_port = Port(IdString("\\__CONST__"))
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const_port.input = False
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const_port.output = True
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cb = SigBit(State.Sx)
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const_bit = Bit(cb, self.design, self.module, const_node, const_port, 0)
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const_node.ports.append(const_port)
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const_port.bits.append(const_bit)
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self.nodes.append(const_node)
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self.wires.append(const_node)
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log(" Creating cell nodes\n")
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for cell in self.module.selected_cells():
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c = PyCell(self.design, self.module, cell.name, cell)
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for first, second in cell.connections_.items():
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p = Port(first)
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p.input = cell.input(p.name)
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p.output = cell.output(p.name)
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for bit in sigmap(second).to_sigbit_vector():
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b = Bit(bit, self.design, self.module, c, p, len(p.bits))
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p.bits.append(b)
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c.ports.append(p)
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self.cells.append(c)
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log(" Creating wire nodes\n")
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for wire in self.module.selected_wires():
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node = PyWire(self.design, self.module, wire.name)
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p = Port(IdString(""))
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if wire.port_input:
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node.nodeType = NodeType.GRAPH_PI
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p.name = IdString("\\PI")
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p.input = False
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p.output = True
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elif wire.port_output:
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node.nodeType = NodeType.GRAPH_PO
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p.name = IdString("\\PO")
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p.input = True
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p.output = False
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for bit in sigmap(wire).to_sigbit_set():
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b = Bit(bit, self.design, self.module, node, p, len(p.bits))
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p.bits.append(b)
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node.ports.append(p)
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self.wires.append(node)
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self.nodes.extend(self.cells)
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self.nodes.extend(wire for wire in self.wires if wire.nodeType in [NodeType.GRAPH_PI, NodeType.GRAPH_PO])
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log(" Creating node index for fast lookup\n")
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idx = 0
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for node in self.nodes:
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self.node_index[node.name] = idx
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idx += 1
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log(" Creating node bits (= const + cell + PI + PO)\n")
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for node in self.nodes:
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for port in node.ports:
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for bit in port.bits:
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self.node_bits.append(bit)
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log(" Creating wire bits\n")
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for wire in self.wires:
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for port in wire.ports:
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for bit in port.bits:
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self.wire_bits.append(bit)
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log(" Creating node bit index for fast lookup\n")
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idx = 0
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for bit in self.node_bits:
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self.node_bit_index[bit] = idx
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idx += 1
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log(" Creating wire bit index for fast lookup\n")
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idx = 0
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for bit in self.wire_bits:
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self.wire_bit_index[bit] = idx
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idx += 1
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log(" Mapping port.wire connections to wire bit index\n")
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idx = 0
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wbitmap = {}
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for wbit in self.wire_bits:
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wbitmap[wbit.bit] = idx
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idx += 1
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inputTriplets = []
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outputTriplets = [(0,0,1)]
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log(" Mapping node bits to wire bits\n")
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idx = 0
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for nbit in self.node_bits:
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row = idx
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idx += 1
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col = 0
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val = 1
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def check_wire():
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nonlocal nbit
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try:
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wire = nbit.bit.wire
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return True
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except:
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return False
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if check_wire() and not self.design.selected_member(self.module.name, self.module.wire(nbit.bit.wire.name).name):
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continue
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if check_wire():
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col = wbitmap[nbit.bit]
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triplet = (row, col, val)
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if col == 0 and row != 0:
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inputTriplets.append(triplet)
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continue
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if nbit.node.nodeType == NodeType.GRAPH_CELL:
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cell = nbit.node
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if check_wire() and self.design.selected_member(self.module.name, self.module.wire(nbit.bit.wire.name).name):
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if cell.cell.input(nbit.port.name):
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inputTriplets.append(triplet)
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if cell.cell.output(nbit.port.name):
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outputTriplets.append(triplet)
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continue
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if nbit.node.nodeType == NodeType.GRAPH_PI and self.design.selected_member(self.module.name, self.module.wire(nbit.bit.wire.name).name):
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outputTriplets.append(triplet)
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continue
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if nbit.node.nodeType == NodeType.GRAPH_PO and self.design.selected_member(self.module.name, self.module.wire(nbit.bit.wire.name).name):
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inputTriplets.append(triplet)
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continue
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log(" Creating port-to-wire incidence matrices\n")
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sizeX = len(self.node_bits)
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sizeY= len(self.wire_bits)
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inputRows = [i[0] for i in inputTriplets]
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inputCols = [i[1] for i in inputTriplets]
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inputVals = [i[2] for i in inputTriplets]
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self.incoming = coo_matrix((inputVals, (inputRows, inputCols)), shape=(sizeX, sizeY), dtype='int32')
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outputRows = [i[0] for i in outputTriplets]
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outputCols = [i[1] for i in outputTriplets]
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outputVals = [i[2] for i in outputTriplets]
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self.outgoing = coo_matrix((outputVals, (outputRows, outputCols)), shape=(sizeX, sizeY), dtype='int32')
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def dot(self):
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log_header(self.design, "Creating 'dot' bipartite module graph representation of module " + self.module.name.str() + "\n")
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log_push()
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bitmap = {}
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ss = "digraph g{\n"
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ss += " rankdir = LR\n"
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nidx = 0
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pidx = 0
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bidx = 0
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cells_wires = []
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cells_wires.extend(self.cells)
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cells_wires.extend(self.wires)
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idx = 0
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for node in cells_wires:
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for port in node.ports:
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for bit in port.bits:
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bitmap[bit] = idx
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idx += 1
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for node in cells_wires:
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ss += " subgraph cluster" + str(nidx) + " {\n"
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ss += " style = \"setlinewidth(2)\";\n"
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ss += " margin = .2;\n"
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ss += " n" + str(node.name.index_)
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def s_cell():
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nonlocal ss
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ss += "[shape=ellipse,label=\"" + str(nidx) + ":"
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ss += unescape_id(node.cell.type) + "\""
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def s_pi():
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nonlocal ss
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ss += "[shape = box, label=\"" + str(nidx) + ":"
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ss += unescape_id(node.name.str()) + "\""
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def s_po():
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nonlocal ss
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ss += "[shape = diamond, label=\"" + str(nidx) + ":"
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ss += unescape_id(node.name.str()) + "\""
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def s_const():
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nonlocal ss
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ss += "[shape = octagon, label=\"" + str(nidx) + ":CO\""
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def s_wire():
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nonlocal ss
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ss += "[shape = plaintext, label=\"" + str(nidx - len(self.cells)) + ":"
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ss += unescape_id(node.name.str()) + "\""
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switch = {
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NodeType.GRAPH_CELL : s_cell,
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NodeType.GRAPH_PI : s_pi,
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NodeType.GRAPH_PO : s_po,
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NodeType.GRAPH_CONST : s_const,
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NodeType.GRAPH_WIRE : s_wire
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}
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switch[node.nodeType]()
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ss += "];\n"
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pidx = 0
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for port in node.ports:
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ss += " port_" + str(node.name.index_) + "_" + str(port.name.index_)
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ss += "[shape=none,label=<\n"
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ss += " <table border=\"0\" cellborder=\"1\" cellspacing=\"0\" cellpadding=\"4\" >\n"
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ss += " <tr><td bgcolor=\"lightgray\" port=\"p" + str(node.name.index_) + "_"
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ss += str(port.name.index_) + "\"> "
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ss += unescape_id(port.name.str())
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ss += "</td></tr>\n"
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bidx = 0;
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for bit in port.bits:
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ss += " <tr><td bgcolor=\"white\" port=\"b" + str(node.name.index_) + "_" + str(port.name.index_) + "_" + str(bit.pos) + "\"> " + str(bitmap[bit]) + ":" + str(bidx) + "</td></tr>\n"
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bidx += 1
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ss += " </table>\n >];\n"
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if node.nodeType == NodeType.GRAPH_CELL:
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if node.cell.output(port.name):
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ss += " n" + str(node.name.index_) + " -> " + "port_" + str(node.name.index_) + "_" + str(port.name.index_) + ":p" + str(node.name.index_) + "_" + str(port.name.index_) + ";\n"
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else:
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ss += " port_" + str(node.name.index_) + "_" + str(port.name.index_) + ":p" + str(node.name.index_) + "_" + str(port.name.index_) + " -> " + "n" + str(node.name.index_) + ";\n"
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if node.nodeType == NodeType.GRAPH_PI or node.nodeType == NodeType.GRAPH_CONST:
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ss += " n" + str(node.name.index_) + " -> " + "port_" + str(node.name.index_) + "_" + str(port.name.index_) + ":p" + str(node.name.index_) + "_" + str(port.name.index_) + ";\n"
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if node.nodeType == NodeType.GRAPH_PO:
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ss += " port_" + str(node.name.index_) + "_" + str(port.name.index_) + ":p" + str(node.name.index_) + "_" + str(port.name.index_) + " -> " + "n" + str(node.name.index_) + ";\n"
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pidx += 1
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ss += " }\n"
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nidx += 1
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for i in range(len(self.incoming.nonzero()[0])):
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b1 = self.node_bits[self.incoming.nonzero()[0][i]]
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b2 = self.wire_bits[self.incoming.nonzero()[1][i]]
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if b1.node.nodeType == NodeType.GRAPH_PO or b1.node.nodeType == NodeType.GRAPH_CONST:
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continue
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ss += " "
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ss += "port_" + str(b2.node.name.index_) + "_" + str(b2.port.name.index_) + ":"
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ss += "b" + str(b2.node.name.index_) + "_" + str(b2.port.name.index_) + "_" + str(b2.pos)
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ss += " -> "
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ss += "port_" + str(b1.node.name.index_) + "_" + str(b1.port.name.index_) + ":"
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ss += "b" + str(b1.node.name.index_) + "_" + str(b1.port.name.index_) + "_" + str(b1.pos)
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ss += ";\n"
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for i in range(len(self.outgoing.nonzero()[0])):
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b1 = self.node_bits[self.outgoing.nonzero()[0][i]]
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b2 = self.wire_bits[self.outgoing.nonzero()[1][i]]
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if b1.node.nodeType == NodeType.GRAPH_PI:
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continue
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ss += " "
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ss += "port_" + str(b1.node.name.index_) + "_" + str(b1.port.name.index_) + ":"
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ss += "b" + str(b1.node.name.index_) + "_" + str(b1.port.name.index_) + "_" + str(b1.pos)
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ss += " -> "
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ss += "port_" + str(b2.node.name.index_) + "_" + str(b2.port.name.index_) + ":"
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ss += "b" + str(b2.node.name.index_) + "_" + str(b2.port.name.index_) + "_" + str(b2.pos)
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ss += ";\n"
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ss += "}\n"
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log_pop()
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return ss
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def save_dot(self, filename):
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savetxt(filename, [self.dot()], fmt="%s")
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def save_incoming(self, filename, delimiter = ","):
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savetxt(filename, self.incoming.todense(), "%d", delimiter=delimiter)
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def save_outgoing(self, filename, delimiter = ","):
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savetxt(filename, self.outgoing.todense(), "%d", delimiter=delimiter)
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def save_adjacency(self, filename, delimiter = ","):
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savetxt(filename, (self.outgoing*self.incoming.transpose()).todense(), "%d", delimiter=delimiter)
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p = None
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class NetlistGraphPass(Pass):
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def __init__(self):
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super().__init__("netlist_graph", "Generates the Netlist-Graph of a module")
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import argparse
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self.parser = argparse.ArgumentParser()
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self.parser.add_argument("-mod", nargs=1, metavar="MOD", help="The Netlist-Graph of the module with the id-string <module> will be generated. If this argument is not given, the first module will be used")
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self.parser.add_argument("-dot", nargs=1, metavar="FILE", help="Write the Netlist-Graph to FILE in dot format")
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self.parser.add_argument("-i","-incoming", nargs=1, metavar="FILE", help="Write the incoming incidence matrix to FILE in csv format")
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self.parser.add_argument("-o","-outgoing", nargs=1, metavar="FILE", help="Write the outgoing incidence matrix to FILE in csv format")
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self.parser.add_argument("-a","-adjacency", nargs=1, metavar="FILE", help="Write the adjacency matrix to FILE in csv format")
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def py_help(self):
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log("This pass generates the Netlist-Graph of a module\n")
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log(self.parser.format_help())
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def py_execute(self, args, des):
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args = self.parser.parse_args(args[1:])
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graph = None
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if args.mod:
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try:
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graph = NetlistGraph(des, des.modules_[IdString(args.mod[0])])
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except KeyError:
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log("Module \"" + args.mod[0] + "\" not found!\n")
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exit()
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else:
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graph = NetlistGraph(des, list(des.modules_.values())[0])
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if args.dot:
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graph.save_dot(args.dot[0])
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if args.i:
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graph.save_incoming(args.i[0])
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if args.o:
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graph.save_outgoing(args.o[0])
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if args.a:
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graph.save_adjacency(args.a[0])
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def py_clear_flags(self):
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log("Clear\n")
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if __name__ == "__main__":
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designs = {}
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graphs = {}
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testdir = "../../tests/simple/"
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import os
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for testcase in os.listdir(testdir):
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if not testcase.endswith(".v"):
|
||||
continue
|
||||
designs[testcase] = Design()
|
||||
run_pass("read_verilog " + testdir + testcase, designs[testcase])
|
||||
run_pass("hierarchy -check -auto-top", designs[testcase])
|
||||
run_pass("proc", designs[testcase])
|
||||
run_pass("clean", designs[testcase])
|
||||
run_pass("memory", designs[testcase])
|
||||
run_pass("clean", designs[testcase])
|
||||
run_pass("opt -full", designs[testcase])
|
||||
run_pass("clean", designs[testcase])
|
||||
graphs[testcase] = NetlistGraph(designs[testcase])
|
||||
|
||||
file_prefix = "out/" + testcase
|
||||
graphs[testcase].save_dot(file_prefix + ".dot")
|
||||
graphs[testcase].save_incoming(file_prefix + "_in.csv")
|
||||
graphs[testcase].save_outgoing(file_prefix + "_out.csv")
|
||||
graphs[testcase].save_adjacency(file_prefix + "_adjacency.csv")
|
||||
|
||||
else:
|
||||
p = NetlistGraphPass()
|
||||
|
|
@ -0,0 +1,32 @@
|
|||
#!/usr/bin/python3
|
||||
|
||||
from pyosys import libyosys as ys
|
||||
|
||||
import matplotlib.pyplot as plt
|
||||
import numpy as np
|
||||
|
||||
class CellStatsPass(ys.Pass):
|
||||
|
||||
def __init__(self):
|
||||
super().__init__("cell_stats", "Shows cell stats as plot")
|
||||
|
||||
def py_help(self):
|
||||
ys.log("This pass uses the matplotlib library to display cell stats\n")
|
||||
|
||||
def py_execute(self, args, design):
|
||||
ys.log_header(design, "Plotting cell stats\n")
|
||||
cell_stats = {}
|
||||
for module in design.selected_whole_modules_warn():
|
||||
for cell in module.selected_cells():
|
||||
if cell.type.str() in cell_stats:
|
||||
cell_stats[cell.type.str()] += 1
|
||||
else:
|
||||
cell_stats[cell.type.str()] = 1
|
||||
plt.bar(range(len(cell_stats)), height = list(cell_stats.values()),align='center')
|
||||
plt.xticks(range(len(cell_stats)), list(cell_stats.keys()))
|
||||
plt.show()
|
||||
|
||||
def py_clear_flags(self):
|
||||
ys.log("Clear Flags - CellStatsPass\n")
|
||||
|
||||
p = CellStatsPass()
|
||||
|
|
@ -1,6 +0,0 @@
|
|||
PYTHONPATH=`pwd`/../../:$PYTHONPATH
|
||||
mkdir -p out
|
||||
if [ ! -f ../../libyosys.so ]; then
|
||||
make -C ../..
|
||||
fi
|
||||
python3.5 netlist_graph.py
|
||||
|
|
@ -0,0 +1,22 @@
|
|||
#!/usr/bin/python3
|
||||
|
||||
from pyosys import libyosys as ys
|
||||
|
||||
import matplotlib.pyplot as plt
|
||||
import numpy as np
|
||||
|
||||
design = ys.Design()
|
||||
ys.run_pass("read_verilog ../../tests/simple/fiedler-cooley.v", design);
|
||||
ys.run_pass("prep", design)
|
||||
ys.run_pass("opt -full", design)
|
||||
|
||||
cell_stats = {}
|
||||
for module in design.selected_whole_modules_warn():
|
||||
for cell in module.selected_cells():
|
||||
if cell.type.str() in cell_stats:
|
||||
cell_stats[cell.type.str()] += 1
|
||||
else:
|
||||
cell_stats[cell.type.str()] = 1
|
||||
plt.bar(range(len(cell_stats)), height = list(cell_stats.values()),align='center')
|
||||
plt.xticks(range(len(cell_stats)), list(cell_stats.keys()))
|
||||
plt.show()
|
||||
Loading…
Reference in New Issue