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4865 Commits

Author SHA1 Message Date
Clifford Wolf ee68b4d963 Merge branch 'master' of github.com:YosysHQ/yosys 2018-07-16 15:32:38 +02:00
Clifford Wolf f39b897545 Add "read -incdir" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-07-16 15:32:26 +02:00
David Shah e9ef077266 ecp5: Fixing 'X' issues with LUT simulation models 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-07-16 15:20:34 +02:00
David Shah b2c62ff8ef ecp5: ECP5 synthesis fixes 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-07-16 14:33:13 +02:00
David Shah 459d367913 ecp5: Adding synchronous set/reset support 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-07-14 16:18:01 +02:00
David Shah 241429abac ecp5: Add DRAM match rule 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-07-13 16:25:52 +02:00
David Shah 4a60bc83ab ecp5: Cells and mappings fixes 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-07-13 16:14:08 +02:00
David Shah b0fea67cc6 ecp5: Fixing arith_map 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-07-13 15:49:59 +02:00
David Shah 11c916840d ecp5: Initial arith_map implementation 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-07-13 15:46:12 +02:00
David Shah c2d7be140a ecp5: Adding basic synth_ecp5 based on synth_ice40 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-07-13 14:52:25 +02:00
David Shah eb8f3f7dc4 ecp5: Adding DFF maps 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-07-13 14:32:23 +02:00
Clifford Wolf db4514944d
Merge pull request #580 from daveshah1/ice40_nx 
ice40: Add CIN_CONST and CIN_SET parameters to ICESTORM_LC
 2018-07-13 14:31:38 +02:00
David Shah 1def34f2a6 ecp5: Adding DRAM map 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-07-13 14:08:42 +02:00
David Shah b1b9e23f94 ecp5: Adding basic cells_sim and mapper for LUTs up to LUT7 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-07-13 13:27:24 +02:00
David Shah cd65eeb3b3 ice40: Add CIN_CONST and CIN_SET parameters to ICESTORM_LC 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-07-13 13:09:18 +02:00
Benedikt Tutzer 0371519c39 Added Monitor class that can monitor all changes in a Design or in a Module 2018-07-10 12:51:02 +02:00
Benedikt Tutzer e7d3f3cd46 added destructors for wires and cells 2018-07-10 08:52:36 +02:00
Benedikt Tutzer 55df7fff19 removed debug output 2018-07-09 16:02:10 +02:00
Benedikt Tutzer da8083dbd0 commands can now be run on arbitrary designs, not only on the active one 2018-07-09 16:01:56 +02:00
Benedikt Tutzer 8ebaeecd83 multiple designs can now exist independent from each other. Cells/Wires/Modules can now move to a different parent without referencing issues 2018-07-09 15:48:06 +02:00
William D. Jones 0caa62802c Gate POSIX-only signals and resource module to only run on POSIX Python implementations. 2018-07-06 01:44:34 -04:00
Aman Goel f0b1ec3e97 Merge branch 'YosysHQ-master' 2018-07-04 15:14:58 -04:00
Aman Goel 4d343fc1cd Merging with official repo 2018-07-04 15:14:28 -04:00
Clifford Wolf 8b92ddb9d2 Fix verific eventually handling 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-06-29 19:24:58 +02:00
Clifford Wolf 0404cf61d5 Add verific support for eventually properties 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-06-29 19:21:04 +02:00
Clifford Wolf ebf0f003d3 Add "verific -formal" and "read -formal" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-06-29 10:02:27 +02:00
Clifford Wolf afedb2d03e Add "read -sv -D" support 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-06-28 23:58:15 +02:00
Clifford Wolf 07e616900c Add "read -undef" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-06-28 23:43:38 +02:00
Clifford Wolf fe2ee833e1 Fix handling of signed memories 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-06-28 16:57:03 +02:00
Benedikt Tutzer 7911379d4a Introduced namespace and removed class-prefixes to increase readability 2018-06-28 15:07:21 +02:00
Benedikt Tutzer ccb4dcd013 changed references from hash-ids to IdString names 2018-06-28 14:44:28 +02:00
William D. Jones 7e5801beed Add support for 64-bit builds using msys2 environment. 2018-06-27 16:36:18 -04:00
William D. Jones ee7164b879 Use msys2-provided pthreads instead of abc's. 2018-06-27 16:26:36 -04:00
Benedikt Tutzer a27fa1833e added wrappers for Design, Modules, Cells and Wires 2018-06-25 17:08:29 +02:00
Clifford Wolf 848c3c5c88 Add YOSYS_NOVERIFIC env variable for temporarily disabling verific 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-06-22 20:40:22 +02:00
Benedikt Tutzer 4d4117c998 added ENABLE_PYTHON option in build environment 2018-06-22 11:15:03 +02:00
Clifford Wolf d412b17259 Add simplified "read" command, enable extnets in implicit Verific import 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-06-21 16:56:55 +02:00
Clifford Wolf 9e096b1512 Merge branch 'master' of github.com:YosysHQ/yosys 2018-06-20 23:45:26 +02:00
Clifford Wolf 5f2bc1ce76 Add automatic verific import in hierarchy command 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-06-20 23:45:01 +02:00
Clifford Wolf c1d6934663
Merge pull request #572 from q3k/q3k/fix-protobuf-build 
Fix protobuf build
 2018-06-20 20:40:59 +02:00
Sergiusz Bazanski 1690dafde1 Fix protobuf build 2018-06-20 19:28:43 +01:00
Clifford Wolf 626b555244
Merge pull request #571 from q3k/q3k/protobuf-backend 
Add Protobuf backend
 2018-06-19 15:02:04 +02:00
Serge Bazanski 53e9a1549c Add Protobuf backend 
Signed-off-by: Serge Bazanski <q3k@symbioticeda.com>
 2018-06-19 13:34:56 +01:00
Clifford Wolf 675a44b41a Be slightly less aggressive in "deminout" pass 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-06-19 14:29:38 +02:00
Clifford Wolf 25c5002f83
Merge pull request #570 from edcote/patch-4 
Include module name for area summary stats
 2018-06-19 13:47:39 +02:00
Edmond Cote d89560a0ba
Include module name for area summary stats 
The PR prints the name of the module when displaying the final area count.

Pros:
- Easier for the user to `grep` for area information about a specific module

Cons:
- Arguably more verbose, less "pretty" than author desires

Verification:
~~~~
30c30
<    Chip area for this module: 20616.349000
---
>    Chip area for module '$paramod$d1738fc0bb353d517bc2caf8fef2abb20bced034\picorv32': 20616.349000
70c70
<    Chip area for this module: 88.697700
---
>    Chip area for module '\picorv32_axi_adapter': 88.697700
102c102
<    Chip area for this module: 20705.046700
---
>    Chip area for top module '\picorv32_axi': 20705.046700
~~~~
 2018-06-18 17:29:01 -07:00
Clifford Wolf 0ff0ce4973 Bugfix in liberty parser (as suggested by aiju in #569) 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-06-15 18:56:44 +02:00
Clifford Wolf 57fc8dd582 Add "synth_ice40 -json" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-06-13 13:35:10 +02:00
Clifford Wolf 83631555dd Fix ice40_opt for cases where a port is connected to a signal with width != 1 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-06-11 18:12:42 +02:00
Udi Finkelstein 8b7580b0a1 Detect illegal port declaration, e.g input/output/inout keyword must be the first. 2018-06-06 22:27:25 +03:00