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Merge branch 'master' of github.com:YosysHQ/yosys

This commit is contained in:
Clifford Wolf 2018-07-16 15:32:38 +02:00
parent f39b897545 db4514944d
commit ee68b4d963
1 changed files with 6 additions and 2 deletions
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8
techlibs/ice40/cells_sim.v
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@ -657,7 +657,12 @@ module ICESTORM_LC (
parameter [0:0] SET_NORESET = 0;
parameter [0:0] ASYNC_SR = 0;
assign COUT = CARRY_ENABLE ? (I1 && I2) || ((I1 || I2) && CIN) : 1'bx;
parameter [0:0] CIN_CONST = 0;
parameter [0:0] CIN_SET = 0;
wire mux_cin = CIN_CONST ? CIN_SET : CIN;
assign COUT = CARRY_ENABLE ? (I1 && I2) || ((I1 || I2) && mux_cin) : 1'bx;
wire [7:0] lut_s3 = I3 ? LUT_INIT[15:8] : LUT_INIT[7:0];
wire [3:0] lut_s2 = I2 ? lut_s3[ 7:4] : lut_s3[3:0];
@ -1226,4 +1231,3 @@ module SB_IO_OD (
endgenerate
`endif
endmodule