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3085 Commits

Author SHA1 Message Date
rodrigosiqueira 3f2f64f414 Added explanation about configure and create test 
Added explanation about configure unit test environment and how to add new unit tests
 2016-12-04 11:35:13 -02:00
rodrigosiqueira e0152319f5 Added required structure to implement unit tests 
Added modifications inside the main Makefile to refers the unit test Makefile.
Added separated Makefile only for compiling unit tests.
Added simple example of unit test.

Signed-off-by: Charles Oliveira <18oliveira.charles@gmail.com>
Signed-off-by: Pablo Alejandro <pabloabur@usp.br>
Signed-off-by: Rodrigo Siqueira <siqueira@ime.usp.br>
 2016-12-04 11:34:27 -02:00
Clifford Wolf a44cc7a3d1 Added $assert/$assume support to AIGER back-end 2016-12-03 13:20:29 +01:00
Clifford Wolf 37760541bd Improved yosys-smtbmc default -t/--assume-skipped for --cex and --aig 2016-12-03 12:37:20 +01:00
Clifford Wolf 8a90e61c1a Updated ABV to hg rev 8b555d9e67cf 2016-12-01 17:45:40 +01:00
Clifford Wolf 105b6374ae Added examples/aiger/ 2016-12-01 13:42:17 +01:00
Clifford Wolf 88b9733253 Added "yosys-smtbmc --aig" 2016-12-01 13:16:57 +01:00
Clifford Wolf 52c243cf05 Added support for partially initialized regs to smt2 back-end 2016-12-01 12:00:00 +01:00
Clifford Wolf 5fa1fa1e6f Added "write_aiger -zinit -symbols -vmap" 2016-12-01 11:04:36 +01:00
Clifford Wolf c1f762ca56 Added "write_aiger" command 2016-11-30 21:30:24 +01:00
Clifford Wolf b1cdf772eb Added "design -reset-vlog" 2016-11-30 11:25:55 +01:00
Clifford Wolf ac7a175a3c Improved equiv_purge log output 2016-11-29 13:30:35 +01:00
Clifford Wolf df2e5aad6f Bugfix in smt2 back-end for pure checker modules 2016-11-28 15:15:09 +01:00
Clifford Wolf ecdc22b06c Added support for macros as include file names 2016-11-28 14:50:17 +01:00
Clifford Wolf c7f6fb6e17 Bugfix in "read_verilog -D NAME=VAL" handling 2016-11-28 14:45:05 +01:00
Clifford Wolf c17d98f55c Removed shebang line from smtio.py, fixes #279 2016-11-27 12:11:04 +01:00
Clifford Wolf 5c2c78e2dd Added wire start_offset and upto handling BLIF back-end 2016-11-23 13:54:33 +01:00
Clifford Wolf e444e59963 Added wire start_offset and upto handling to splitnets cmd 2016-11-23 13:54:33 +01:00
Clifford Wolf 73653de5ff Merge pull request #274 from oldtopman/lcurses 
Added optional flag for linking curses with readline.
 2016-11-22 21:24:45 +01:00
Clifford Wolf f257ccf22e Added "yosys-smtbmc --append" 2016-11-22 21:21:13 +01:00
oldtopman 277f478572 Added optional flag for linking curses with readline. 2016-11-21 23:11:58 -07:00
Clifford Wolf 3b73d3f140 Merge pull request #272 from AlexDaniel/master 
Markdownify README (№2)
 2016-11-19 23:25:58 +01:00
Aleks-Daniel Jakimenko-Aleksejev 3c86da8000
Keep lines under 80 characters 
Recent README changes added some characters to existing lines, which
made them longer than 80 characters. This commit fixes that.
 2016-11-19 20:51:50 +02:00
Clifford Wolf 55785a96eb Improved ABC default scripts 2016-11-19 18:20:54 +01:00
Aleks-Daniel Jakimenko-Aleksejev 751ad3c618
Markdownify README even further 2016-11-19 19:07:02 +02:00
Clifford Wolf 487b19b4fa Merge pull request #271 from azidar/bugfix-assign-wmask 
Bugfix: include assign to write-mask
 2016-11-19 17:36:07 +01:00
Adam Izraelevitz f77dc3bacc Bugfix: include assign to write-mask 2016-11-18 11:49:26 -08:00
Clifford Wolf e01382739d More progress in FIRRTL back-end 2016-11-18 02:41:29 +01:00
Clifford Wolf c051115e03 Progress in FIRRTL back-end 2016-11-18 00:32:35 +01:00
Clifford Wolf 57966a619f Added first draft of FIRRTL back-end 2016-11-17 23:36:47 +01:00
Clifford Wolf ce132cf652 Cleanups and fixed in write_verilog regarding reg init 2016-11-16 12:00:39 +01:00
Clifford Wolf 70d7a02cae Added support for hierarchical defparams 2016-11-15 13:35:19 +01:00
Clifford Wolf a926a6afc2 Remember global declarations and defines accross read_verilog calls 2016-11-15 12:42:43 +01:00
Clifford Wolf a2206180d6 Merge pull request #268 from AlexDaniel/master 
Markdownify README
 2016-11-13 21:47:51 +01:00
Aleks-Daniel Jakimenko-Aleksejev d4e1592609
Markdownify README 
This is the first commit in series. There are many other things that
could be improved, this is just the first renderable version.
 2016-11-12 23:33:28 +02:00
Clifford Wolf 1827a48964 Minor bugfix in submod 2016-11-09 13:13:26 +01:00
Clifford Wolf 617693e691 Progress in examples/gowin/ 2016-11-08 19:07:22 +01:00
Clifford Wolf e9d73d2ee0 Indenting fixes in gowin sim cell lib 2016-11-08 18:54:00 +01:00
Clifford Wolf 97ac77513f Bugfix in "setundef" pass 2016-11-08 18:53:36 +01:00
Clifford Wolf 84badc97b3 Added examples/gowin/ 2016-11-07 12:55:56 +01:00
Clifford Wolf ef603c6fe1 Implemented "scc -set_attr" 2016-11-06 00:04:10 +01:00
Clifford Wolf 914aa8a5d3 Bugfix in "scc" command 2016-11-06 00:03:35 +01:00
Clifford Wolf 2874914bcb Fixed anonymous genblock object names 2016-11-04 07:46:30 +01:00
Clifford Wolf 3db2ac4e00 Added hex constant support to write_verilog 2016-11-03 12:13:23 +01:00
Clifford Wolf e3330fb98f We are now in 0.7+ development 2016-11-03 10:31:51 +01:00
Clifford Wolf 61f6811627 Yosys 0.7 2016-11-03 09:08:43 +01:00
Clifford Wolf 308a4b4a1b Bugfix in "hierarchy -check" 2016-11-02 20:09:57 +01:00
Clifford Wolf 4832faf5e9 Updated command reference in manual 2016-11-02 19:25:28 +01:00
Clifford Wolf 8e48685706 Changelog for Yosys 0.7 2016-11-02 18:53:30 +01:00
Clifford Wolf b63cace90f Added support for fsm_encoding="user" 2016-11-02 13:15:49 +01:00