yosys

Commit Graph

Author	SHA1	Message	Date
Eddie Hung	592baebd22	xilinx: xilinx_dsp_cascade to check CREG for DSP48E1 only	2020-04-22 17:43:25 -07:00
Eddie Hung	7f33a0294b	Cleanup use of hard-coded default parameters in light of #1945	2020-04-22 12:02:30 -07:00
Marcin Kościelnicki	e226a8f7f1	Minor nit fixes	2019-12-25 15:39:40 +01:00
Eddie Hung	1d0ac659ad	Fix OPMODE for PCIN->PCOUT cascades in xc6s, check B[01]REG too	2019-12-23 14:40:59 -08:00
Eddie Hung	75acaff6f5	Fix CEA/CEB check	2019-12-23 14:22:13 -08:00
Eddie Hung	edabe73377	Fix checking CE[AB] and for direct connections	2019-12-23 13:41:26 -08:00
Eddie Hung	71cac30309	Support unregistered cascades for A and B inputs	2019-12-23 12:38:18 -08:00
Eddie Hung	d00533eaa8	Add DSP48A* PCOUT -> PCIN cascade support	2019-12-23 11:42:46 -08:00
Eddie Hung	991c2ca95b	Add comment on why we have to match for clock-enable/reset muxes	2019-10-05 08:56:37 -07:00
Eddie Hung	792cd31052	Add comments for xilinx_dsp_cascade	2019-10-04 22:31:04 -07:00
Eddie Hung	aebbfffd71	Ooops AREG and BREG to default to -1	2019-09-27 11:57:53 -07:00
Eddie Hung	5b9deef10d	Do not always zero out C (e.g. during cascade breaks)	2019-09-26 13:59:05 -07:00
Eddie Hung	58f31096ab	Zero out ports	2019-09-26 13:40:38 -07:00
Eddie Hung	af59856ba1	xilinx_dsp_cascade to also cascade AREG and BREG	2019-09-26 13:29:18 -07:00
Eddie Hung	832216dab0	Try recursive pmgen for P cascade	2019-09-26 12:09:57 -07:00
Eddie Hung	d0dbbc2605	Move unextend initialisation later	2019-09-23 13:26:34 -07:00
Eddie Hung	95644b00cb	OPMODE is port not param	2019-09-20 12:37:29 -07:00
Eddie Hung	0bca366bcd	WIP for xiinx_dsp_cascadeAB	2019-09-20 12:07:14 -07:00
Eddie Hung	ed187ef1cf	Add a xilinx_dsp_cascade matcher for PCIN -> PCOUT	2019-09-20 10:00:09 -07:00

19 Commits