riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
3,273 Commits 75 Branches 48 Tags 60 MiB
Commit Graph

3273 Commits

Author SHA1 Message Date
Clifford Wolf 3bbac5c141 Fix equiv_simple, old behavior now available with "equiv_simple -short" 2017-04-28 18:57:53 +02:00
Clifford Wolf f0db8ffdbc Add support for `resetall compiler directive 2017-04-26 16:09:41 +02:00
Clifford Wolf b72a7e1104 Replace CRLF line endings with LF in de2i.qsf (quartus example) 2017-04-12 16:51:46 +02:00
Larry Doolittle 2021ddecb3 Squelch trailing whitespace 2017-04-12 15:11:09 +02:00
Clifford Wolf 41d4e91f38 Add MAX10 and Cyclone IV items to CHANGELOG 2017-04-07 10:01:28 +02:00
Clifford Wolf 7791888703 Merge pull request #337 from dh73/master 
Add initial support for both MAX10 and Cyclone IV (E|GX) FPGAs
 2017-04-07 09:58:54 +02:00
dh73 c27dcc1e47 Add initial support for both MAX10 and Cyclone IV (E|GX) FPGAs 2017-04-05 23:01:29 -05:00
Clifford Wolf fcb274a564 Add ConstEval defaultval feature 2017-04-05 11:25:22 +02:00
Clifford Wolf dee4ec1661 Fix gcc compiler warning 2017-04-05 11:21:06 +02:00
Clifford Wolf b8d7f57f61 Add front-end detection for *.tcl files 2017-03-28 12:13:58 +02:00
Clifford Wolf 58ee8e3b8a Add minisat 00_PATCH_typofixes.patch 2017-03-27 14:37:00 +02:00
Clifford Wolf 71cbe98a09 Remove use of <fpu_control.h> in minisat 2017-03-27 14:32:43 +02:00
Clifford Wolf 106e44f406 Add "write_smt2 -stdt" mode 2017-03-20 12:00:35 +01:00
Clifford Wolf 0ac72e759d Add generation of logic cells to EDIF back-end runtest.py 2017-03-19 14:57:40 +01:00
Clifford Wolf 850f8299a9 Fix EDIF: portRef member 0 is always the MSB bit 2017-03-19 14:53:28 +01:00
Clifford Wolf 1390e9a0a7 Add simple EDIF test case generator and checker 2017-03-18 15:00:03 +01:00
Clifford Wolf 088f9c9cab Fix verilog pre-processor for multi-level relative includes 2017-03-14 17:30:20 +01:00
Clifford Wolf c855353986 Improve smt2 encodings of assert/assume/cover, better wire_smt2 help msg 2017-03-04 23:41:54 +01:00
Clifford Wolf a6ca28276e Add write_aiger $anyseq support 2017-03-02 16:39:48 +01:00
Clifford Wolf 5b3b5ffc8c Allow $anyconst, etc. in non-formal SV mode 2017-03-01 10:47:05 +01:00
Clifford Wolf 180d704568 Disable opt_merge for $anyseq and $anyconst 2017-02-28 22:17:00 +01:00
Clifford Wolf fbd52ec6dd Use hex addresses in smtbmc vcd mem traces 2017-02-28 13:54:50 +01:00
Clifford Wolf 1a6c02a532 Add "chformal -assert2assume" and friends 2017-02-28 00:00:44 +01:00
Clifford Wolf db7fc0e32d Add "chformal" pass 2017-02-27 13:25:28 +01:00
Clifford Wolf 2203562268 Add smtbmc support for memory vcd dumping 2017-02-26 21:26:32 +01:00
Clifford Wolf 80ecd7a26f Fix extra newline bug in write_smt2 2017-02-26 14:41:27 +01:00
Clifford Wolf 6e152f7aa1 Fix bug in smtio unroll code 2017-02-26 14:39:07 +01:00
Clifford Wolf 66a1617b69 Fix assert checking in "yosys-smtbmc -c --append" 2017-02-26 11:06:26 +01:00
Clifford Wolf fd1cc0c73d Improve (and fix for stbv mode) SMT2 memory API 2017-02-26 10:58:34 +01:00
Clifford Wolf 38bf458037 Add support for "yosys-smtbmc -c --append" 2017-02-25 23:41:40 +01:00
Clifford Wolf d6858ad15b Update ABC to hg rev 3a95bfa55df7 2017-02-25 22:59:34 +01:00
Clifford Wolf eec2df6ad1 Merge branch 'klammerj-master' 2017-02-25 16:36:23 +01:00
Clifford Wolf c7d1286728 Improve "write_edif" help message 2017-02-25 16:35:53 +01:00
Clifford Wolf dfddf391f9 Move EdifNames out of double-private namespace 2017-02-25 16:29:27 +01:00
Clifford Wolf 8c61ecdd6e Clean up edif code, swap bit indexing of "upto" ports 2017-02-25 16:28:34 +01:00
Clifford Wolf b76c89a5dd Merge branch 'master' of https://github.com/klammerj/yosys into klammerj-master 2017-02-25 15:59:02 +01:00
Clifford Wolf f3324ed0cc Merge branch 'master' of github.com:cliffordwolf/yosys 2017-02-25 13:08:27 +01:00
Clifford Wolf dac0842d61 Add $live and $fair support to AIGER back-end. 2017-02-25 13:07:15 +01:00
Clifford Wolf 5f1d0b1024 Add $live and $fair cell types, add support for s_eventually keyword 2017-02-25 10:36:39 +01:00
Clifford Wolf 931d775b0b Merge pull request #322 from azonenberg/master 
Add POUT to GP_COUNTx cells
 2017-02-24 19:23:29 +01:00
Clifford Wolf 7af9727f78 Add "write_smt2 -stbv" 2017-02-24 18:24:53 +01:00
Andrew Zonenberg 1f824fa643 Merge https://github.com/cliffordwolf/yosys 2017-02-24 08:12:45 -08:00
Clifford Wolf a9c3acf5a2 Add SMT2 statebv mode (inactive for now) 2017-02-24 14:04:52 +01:00
Johann Klammer 6d7a77dbf6 Did as you requested, /but/... 
Now the nets are wired in reverse again because the netlister still uses zero-based indices.
 2017-02-24 13:18:49 +01:00
Clifford Wolf f648b7cf79 Merge pull request #320 from joshhead/uninstall-binpath-fix 
Add missing slashes in paths for make uninstall
 2017-02-24 12:48:12 +01:00
Josh Headapohl fde9fdfbe8 Add missing slashes in paths for make uninstall 
Running make uninstall used to fail to remove binaries:
rm -vf /usr/local/binyosys /usr/local/binyosys-config #...etc

Fix Makefile so that it runs a command like this:
rm -vf /usr/local/bin/yosys /usr/local/bin/yosys-config #...etc
 2017-02-23 20:21:03 -05:00
Johann Klammer 06df86aae3 add options for edif flavors 
*to force renames on wide ports
*to choose array delimiters
*to choose up or downwards indices
 2017-02-23 19:42:37 +01:00
Clifford Wolf 00dba4c197 Add support for SystemVerilog unique, unique0, and priority case 2017-02-23 16:33:19 +01:00
Clifford Wolf 1e927a51d5 Preserve string parameters 2017-02-23 15:39:13 +01:00
Clifford Wolf c6d8d70109 Fix mingw compile issue (2nd attempt) 2017-02-23 14:21:02 +01:00