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12815 Commits

Author SHA1 Message Date
github-actions[bot] 373b651d5b Bump version 2023-12-10 00:17:47 +00:00
Merry 0681baae19 cxxrtl: Extract divmod algorithm into value 2023-12-09 19:23:04 +00:00
Merry 99c8143ded cxxrtl: Remove redundant divmod 2023-12-09 19:23:04 +00:00
Martin Povišer e6021b2b48
Merge pull request #4057 from jix/peepopt_shiftmul_right_padding_fix 
peepopt: Fix padding for the peepopt_shiftmul_right pattern
 2023-12-07 14:56:53 +01:00
github-actions[bot] fb4cbfa735 Bump version 2023-12-07 00:16:21 +00:00
Jannis Harder 7b74caa5db peepopt: Fix padding for the peepopt_shiftmul_right pattern 
The previous version could easily generate a large amount of padding
when the constant factor was significantly larger than the width of the
shift data input. This could lead to huge amounts of logic being
generated before then being optimized away at a huge performance and
memory cost.

Additionally and more critically, when the input width was not a
multiple of the constant factor, the input data was padded with 'x bits
to such a multiple before interspersing the 'x padding needed to align
the selectable windows to power-of-two offsets.

Such a final padding would not be correct for shifts besides $shiftx,
and the previous version did attempt to remove that final padding at the
end so that the native zero/sign/x-extension behavior of the shift cell
would be used, but since the last selectable window also got
power-of-two padding appended after the padding the code is trying to
remove got added, it did not actually fully remove it in some cases.

I changed the code to only add 'x padding between selectable windows,
leaving the last selectable window unpadded. This omits the need to add
final padding to a multiple of the constant factor in the first place.
In turn, that means the only 'x bits added are actually impossible to
select. As a side effect no padding is added when the constant factor is
equal to or larger than the width of the shift data input, also solving
the reported performance bug.

This fixes #4056
 2023-12-06 18:35:44 +01:00
Miodrag Milanović 45dd9eca64
Merge pull request #4051 from YosysHQ/wasi_ci 
Add WASI CI build
 2023-12-06 10:52:13 +01:00
Miodrag Milanovic 6dc62bd013 Fix out of tree build 2023-12-06 09:56:35 +01:00
Miodrag Milanovic 56abf92b85 Add WASI CI build 2023-12-06 09:19:11 +01:00
Miodrag Milanovic d71dd5b9bb Fix out of tree build 2023-12-06 09:11:51 +01:00
github-actions[bot] a530321042 Bump version 2023-12-06 00:16:15 +00:00
Martin Povišer 093f9c7bac
Merge pull request #4053 from povik/pmgen-make 
pmgen: Have a single make pattern
 2023-12-05 19:56:09 +01:00
Martin Povišer 16ea497d7c pmgen: Have a single make pattern 
Remove duplicate %.pmg -> %_pm.h pattern. One of the duplicates overrode
the other, and in some conditions there were build races as to whether
the target directory for the generated header would exist. Instead have
a single rule which is properly generalized.
 2023-12-05 18:30:13 +01:00
Miodrag Milanovic 0ccff57062 Next dev cycle 2023-12-05 08:58:28 +01:00
Miodrag Milanovic 8f07a0d840 Release version 0.36 2023-12-05 08:55:12 +01:00
github-actions[bot] 2ffea67b04 Bump version 2023-12-05 00:16:14 +00:00
Martin Povišer b1bbb5827a
Merge pull request #4050 from povik/ql-bram_types-gen 
quicklogic: Generate `bram_types_sim.v` at build time
 2023-12-04 20:04:20 +01:00
Martin Povišer e0fc48e196 quicklogic: Generate `bram_types_sim.v` at build time 2023-12-04 18:21:00 +01:00
Miodrag Milanović 8738143880
Merge pull request #4045 from povik/upstream-ql-k6n10f 
Upstream QuickLogic k6n10f flow
 2023-12-04 16:47:17 +01:00
Miodrag Milanovic 96fecf0716 Revert "Add attributes to module instantiation" 
This reverts commit 8f207eed1b.
 2023-12-04 16:37:01 +01:00
Martin Povišer 22cc4aff51 quicklogic: Test TDP36K inference with initial data 2023-12-04 15:52:03 +01:00
Krystine Sherwin e5c32f399a synth_quicklogic: Testing double_sync_ram_tdp 2023-12-04 15:52:03 +01:00
Krystine Sherwin 97354782c0 Adding double_sync_ram_tdp to blockram.v 2023-12-04 15:52:03 +01:00
Krystine Sherwin 215a777eb3 qlf_tests: minor adjustment 
Renamed python script so that it sits next to the testbench file when alphabetically sorted.
Reverted `MAX_WIDTH` to full precision for truncation testing.
 2023-12-04 15:52:03 +01:00
N. Engelhardt 33ca6994b7 remove example test 2023-12-04 15:52:03 +01:00
N. Engelhardt 3c5b0ab164 fix test setup for synth_quicklogic memory tests 2023-12-04 15:52:03 +01:00
Krystine Sherwin 509d176523 attempting to sim split memory tests 
and failing
 2023-12-04 15:52:03 +01:00
Krystine Sherwin 0d1668c1ee QLF_TDP36K: asymmetric simulation tests 2023-12-04 15:52:03 +01:00
Krystine Sherwin 497cd021af QLF_TDP36K: truncation tests matter 
Expected values are now stored in full precision rather than truncating to the same value as the input.
i.e. 0x5a5a5a5a will truncate to 0x5a5a for write data but will remain 0x5a5a5a5a for expected read.
 2023-12-04 15:52:03 +01:00
Krystine Sherwin 7f12d0ba95 QLF_TDP36K: more basic tdp/sdp sim tests 
Adds TDP submodule to generator.
Adds shorthand expected signal to testbench (mostly to make it easier when I look at the vcd dump to figure out what I did wrong in tests).
 2023-12-04 15:52:03 +01:00
Krystine Sherwin 3d08ed216d QLF_TDP36K: parameterised sim test gen 
Also limited to 16 tests per file to allow parallelism.
Previous tests are converted to new test format with no sim test steps.
 2023-12-04 15:52:03 +01:00
Krystine Sherwin ba3be3fd1c QLF_TDP36K: test bram_tdp post synth 2023-12-04 15:52:03 +01:00
N. Engelhardt f9c8978128 add example memory test 2023-12-04 15:52:03 +01:00
Krystine Sherwin ede4eaeee2 quicklogic: wildcard asymmetric memory tests 2023-12-04 15:52:03 +01:00
Krystine Sherwin 8ded7020f4 tests: asymmetric sync rams now correctly asymmetric 
Also both use the same named parameters for better mirroring.
 2023-12-04 15:52:03 +01:00
Krystine Sherwin ba09866217 quicklogic: testing port widths on split rams 2023-12-04 15:52:03 +01:00
Krystine Sherwin 1a843b2a86 quicklogic: testing 1:4 assymetric memory 2023-12-04 15:52:03 +01:00
Krystine Sherwin 7513bfcbfe quicklogic: fix double width read 2023-12-04 15:52:03 +01:00
Krystine Sherwin 8d3b238b9b quicklogic: Testing split TDP36K 
Adds `double_sync_ram_sdp` to `common/blockram.v`, providing a test for two disjoint memories.
Refactor python blockram template to take a list of params to support the above.
Also change the smaller single TDP36K tests to also test `port_a_width` value.
 2023-12-04 15:52:03 +01:00
Krystine Sherwin 991850e1c9 quicklogic: Initial blockram tests 
Use python script to generate tests for both SDP and TDP across multiple sizes of RAM.
Adds sync_ram_sdp_(wwr|wrr) to common blockram.v for double width write and double width read respectively.
 2023-12-04 15:52:03 +01:00
Martin Povišer e0a6a01ecb quicklogic: Add `RAM_INIT` to specialized BRAM models 2023-12-04 15:52:03 +01:00
Martin Povišer 4903f99f85 quicklogic: Add missing `RAM_INIT` param on TDP36K sim model 2023-12-04 15:52:03 +01:00
Martin Povišer b602c0858f quicklogic: Set initial values on inferred TDP36K 2023-12-04 15:52:03 +01:00
Martin Povišer a5c8d246f7 quicklogic: Add k6n10f DSP test 2023-12-04 15:52:03 +01:00
Martin Povišer b30544d61d ql_dsp_io_regs: Fix ID strings, constant detection 2023-12-04 15:52:03 +01:00
Martin Povišer db9e5b4f14 quicklogic: Fix `dffs.ys` test 2023-12-04 15:52:03 +01:00
Martin Povišer dad85b5178 synth_quicklogic: Fix missing FF mapping 2023-12-04 15:52:03 +01:00
Martin Povišer 532aca28ab quicklogic: Drop `blackbox` off `adder_carry` 2023-12-04 15:52:03 +01:00
Martin Povišer 554d8caef7 quicklogic: Add basic k6n10f tests 2023-12-04 15:52:03 +01:00
Martin Povišer e19833f8c7 synth_quiclogic: Fix conditioning of bram passes 2023-12-04 15:52:02 +01:00