mirror of https://github.com/YosysHQ/yosys.git
ql_dsp_io_regs: Fix ID strings, constant detection
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@ -30,9 +30,9 @@ PRIVATE_NAMESPACE_BEGIN
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// ============================================================================
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struct QlDspIORegs : public Pass {
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const std::vector<std::string> ports2del_mult = {"load_acc", "subtract", "acc_fir", "dly_b",
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"saturate_enable", "shift_right", "round"};
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const std::vector<std::string> ports2del_mult_acc = {"acc_fir", "dly_b"};
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const std::vector<IdString> ports2del_mult = {ID(load_acc), ID(subtract), ID(acc_fir), ID(dly_b),
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ID(saturate_enable), ID(shift_right), ID(round)};
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const std::vector<IdString> ports2del_mult_acc = {ID(acc_fir), ID(dly_b)};
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SigMap sigmap;
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@ -80,7 +80,7 @@ struct QlDspIORegs : public Pass {
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// Get DSP configuration
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for (auto cfg_port : {ID(register_inputs), ID(output_select)})
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if (!cell->hasPort(cfg_port) || sigmap(cell->getPort(cfg_port)).is_fully_const())
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if (!cell->hasPort(cfg_port) || !sigmap(cell->getPort(cfg_port)).is_fully_const())
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log_error("Missing or non-constant '%s' port on DSP cell %s\n",
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log_id(cfg_port), log_id(cell));
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int reg_in_i = sigmap(cell->getPort(ID(register_inputs))).as_int();
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@ -97,7 +97,7 @@ struct QlDspIORegs : public Pass {
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log_error("Unexpected feedback configuration on %s\n", log_id(cell));
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// Build new type name
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std::string new_type = "QL_DSP2_MULT";
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std::string new_type = "\\QL_DSP2_MULT";
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// Decide if we should be deleting the clock port
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bool del_clk = true;
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