From b30544d61d575658cff664d7ffbd52f8d7be7c2d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Mon, 27 Nov 2023 17:17:03 +0100 Subject: [PATCH] ql_dsp_io_regs: Fix ID strings, constant detection --- techlibs/quicklogic/ql_dsp_io_regs.cc | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/techlibs/quicklogic/ql_dsp_io_regs.cc b/techlibs/quicklogic/ql_dsp_io_regs.cc index efb1ad4d5..523c86e73 100644 --- a/techlibs/quicklogic/ql_dsp_io_regs.cc +++ b/techlibs/quicklogic/ql_dsp_io_regs.cc @@ -30,9 +30,9 @@ PRIVATE_NAMESPACE_BEGIN // ============================================================================ struct QlDspIORegs : public Pass { - const std::vector ports2del_mult = {"load_acc", "subtract", "acc_fir", "dly_b", - "saturate_enable", "shift_right", "round"}; - const std::vector ports2del_mult_acc = {"acc_fir", "dly_b"}; + const std::vector ports2del_mult = {ID(load_acc), ID(subtract), ID(acc_fir), ID(dly_b), + ID(saturate_enable), ID(shift_right), ID(round)}; + const std::vector ports2del_mult_acc = {ID(acc_fir), ID(dly_b)}; SigMap sigmap; @@ -80,7 +80,7 @@ struct QlDspIORegs : public Pass { // Get DSP configuration for (auto cfg_port : {ID(register_inputs), ID(output_select)}) - if (!cell->hasPort(cfg_port) || sigmap(cell->getPort(cfg_port)).is_fully_const()) + if (!cell->hasPort(cfg_port) || !sigmap(cell->getPort(cfg_port)).is_fully_const()) log_error("Missing or non-constant '%s' port on DSP cell %s\n", log_id(cfg_port), log_id(cell)); int reg_in_i = sigmap(cell->getPort(ID(register_inputs))).as_int(); @@ -97,7 +97,7 @@ struct QlDspIORegs : public Pass { log_error("Unexpected feedback configuration on %s\n", log_id(cell)); // Build new type name - std::string new_type = "QL_DSP2_MULT"; + std::string new_type = "\\QL_DSP2_MULT"; // Decide if we should be deleting the clock port bool del_clk = true;