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Revert "Add attributes to module instantiation" 

This reverts commit 8f207eed1b.
This commit is contained in:
Miodrag Milanovic 2023-12-04 16:37:01 +01:00
parent 8bd681acfc
commit 96fecf0716
1 changed files with 0 additions and 1 deletions
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frontends/verific/verific.cc
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@ -1980,7 +1980,6 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
}
RTLIL::Cell *cell = module->addCell(inst_name, inst_type);
import_attributes(cell->attributes, inst);
if (inst->IsPrimitive() && mode_keep)
cell->attributes[ID::keep] = 1;