From 96fecf0716ed07897dbc87379baa3cdd0b1f0748 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Mon, 4 Dec 2023 16:37:01 +0100 Subject: [PATCH] Revert "Add attributes to module instantiation" This reverts commit 8f207eed1baf85ad185c7139729b10f9756a0041. --- frontends/verific/verific.cc | 1 - 1 file changed, 1 deletion(-) diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index ce687601f..9737fde89 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -1980,7 +1980,6 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma } RTLIL::Cell *cell = module->addCell(inst_name, inst_type); - import_attributes(cell->attributes, inst); if (inst->IsPrimitive() && mode_keep) cell->attributes[ID::keep] = 1;