e9effd58d2
backends/verilog: Support meminit with mask.
2021-07-28 23:18:38 +02:00
a04844bdf8
Merge pull request #2885 from whitequark/cxxrtl-fix-2883
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cxxrtl: treat wires with multiple defs as not inlinable
2021-07-20 13:12:11 +00:00
1a6ddf7892
cxxrtl: treat wires with multiple defs as not inlinable.
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Fixes #2883 .
2021-07-20 10:30:39 +00:00
225af830c1
cxxrtl: treat assignable internal wires used only for debug as locals.
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This issue was introduced in commit 4aa65f40#2739 .
Fixes #2882 .
2021-07-20 10:10:42 +00:00
fc84f23001
cxxrtl: escape colon in variable names in VCD writer.
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The following VCD file crashes GTKWave's VCD loader:
$var wire 1 ! x:1 $end
$enddefinitions $end
In practice, a colon can be a part of a variable name that is
translated from a Verilog function, something like:
update$func$.../hdl/hazard3_csr.v:350$2534.$result
2021-07-19 16:22:55 +00:00
948fc10d7b
cxxrtl: add debug_item::{get,set}.
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Fixes #2877 .
2021-07-18 06:20:45 +00:00
4aa65f406f
cxxrtl: treat internal wires used only for debug as constants.
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Fixes #2739 (again).
2021-07-17 14:23:57 +00:00
2db4137514
Merge pull request #2874 from whitequark/cxxrtl-fix-2589
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cxxrtl: run hierarchy pass regardless of (*top*) attribute presence
2021-07-16 11:12:19 +00:00
efc43270fa
Merge pull request #2873 from whitequark/cxxrtl-fix-2500
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cxxrtl: emit debug items for unused public wires
2021-07-16 11:01:10 +00:00
5b003d6e5c
cxxrtl: run hierarchy pass regardless of (*top*) attribute presence.
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The hierarchy pass does a lot more than just finding the top module,
mainly resolving implicit (positional, wildcard) module connections.
Fixes #2589 .
2021-07-16 10:27:47 +00:00
09218896d6
cxxrtl: emit debug items for unused public wires.
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This greatly improves debug information coverage.
Fixes #2500 .
2021-07-16 10:14:40 +00:00
b28ca7f5ac
cxxrtl: don't expect user cell inputs to be wires.
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Ports can be connected to constants, too. (Usually resets.)
Fixes #2521 .
2021-07-16 09:51:52 +00:00
44a3d924ce
cxxrtl: don't mark buffered internal wires as UNUSED for debug.
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Public wires may alias buffered internal wires, so keep BUFFERED
wires in debug information even if they are private. Debug items are
only created for public wires, so this does not otherwise affect how
debug information is emitted.
Fixes #2540 .
Fixes #2841 .
2021-07-16 07:54:49 +00:00
54b6cb645f
cxxrtl: mark dead local wires as unused even with inlining disabled.
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Fixes #2739 .
2021-07-15 22:27:27 +00:00
8bf9cb407d
kernel/mem: Add a coalesce_inits helper.
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While this helper is already useful to squash sequential initializations
into one in cxxrtl, its main purpose is to squash overlapping masked memory
initializations (when they land) and avoid having to deal with them in
cxxrtl runtime.
2021-07-13 15:59:11 +02:00
4379375d89
Add support for the Bitwuzla solver
2021-07-12 22:07:58 +02:00
37506d737c
cxxrtl: Support memory writes in processes.
2021-07-12 18:27:48 +02:00
af7fa62251
cxxrtl: Add support for memory read port reset.
2021-07-12 18:27:48 +02:00
be5cf29699
cxxrtl: Add support for mem read port initial data.
2021-07-12 18:27:48 +02:00
d5c9595668
cxxrtl: Convert to Mem helpers.
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This *only* does conversion, but doesn't add any new functionality —
support for memory read port init/reset is still upcoming.
2021-07-12 18:27:48 +02:00
2d95a7da9c
Intersynth URL
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Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2021-06-09 12:42:52 +02:00
72787f52fc
Fixing old e-mail addresses and deadnames
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s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi;
s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi;
s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi;
s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi;
s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g ;
2021-06-08 00:39:36 +02:00
cbf6b719fe
Make a few passes auto-call Mem::narrow instead of rejecting wide ports.
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This essentially adds wide port support for free in passes that don't
have a usefully better way of handling wide ports than just breaking
them up to narrow ports, avoiding "please run memory_narrow" annoyance.
2021-05-28 00:40:56 +02:00
055ba748bc
backends/verilog: Add support for memory read port reset and init value.
2021-05-27 23:47:42 +02:00
aabe1c382e
backends/verilog: Add wide port support.
2021-05-27 16:15:46 +02:00
64ba3c3842
backends/verilog: Try to preserve mem write port priorities.
2021-05-26 00:19:31 +02:00
69bf5c81c7
Reject wide ports in some passes that will never support them.
2021-05-25 02:07:25 +02:00
b6721aa9d8
backend/firrtl: Convert to use Mem helpers.
2021-05-24 14:00:33 +02:00
33513d923a
btor: Use is_mem_cell in one more place.
2021-05-23 20:34:52 +02:00
c4cc888b2c
kernel/rtlil: Extract some helpers for checking memory cell types.
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There will soon be more (versioned) memory cells, so handle passes that
only care if a cell is memory-related by a simple helper call instead of
a hardcoded list.
2021-05-22 21:43:00 +02:00
55dc5a4e4f
abc9: fix SCC issues ( #2694 )
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* xilinx: add SCC test for DSP48E1
* xilinx: Gate DSP48E1 being a whitebox behind ALLOW_WHITEBOX_DSP48E1
Have a test that checks it works through ABC9 when enabled
* abc9 to break SCCs using $__ABC9_SCC_BREAKER module
* Add test
* abc9_ops: remove refs to (* abc9_keep *) on wires
* abc9_ops: do not bypass cells in an SCC
* Add myself to CODEOWNERS for abc9*
* Fix compile
* abc9_ops: run -prep_hier before scc
* Fix tests
* Remove bug reference pending fix
* abc9: fix for -prep_hier -dff
* xaiger: restore PI handling
* abc9_ops: -prep_xaiger sigmap
* abc9_ops: -mark_scc -> -break_scc
* abc9: eliminate hard-coded abc9.box from tests
Also tidy up
* Address review
2021-03-29 22:01:57 -07:00
192601385f
rtlil: Fix process memwr roundtrip.
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Fixes #2646 fallout.
2021-03-23 19:49:47 +01:00
6b2100bf01
json: Improve the "processes in module" message a bit.
2021-03-23 15:53:49 +01:00
3d9698153f
json: Add support for memories.
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Previously, memories were silently discarded by the JSON backend, making
round-tripping modules with them crash.
Since there are already some users using JSON to implement custom
external passes that use memories (and infer width/size from memory
ports), let's fix this by just making JSON backend and frontend support
memories as first-class objects.
Processes are still not supported, and will now cause a hard error.
Fixes #1908 .
2021-03-15 17:19:19 +01:00
feff32914b
Merge pull request #2642 from whitequark/cxxrtl-noproc-fixes
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CXXRTL: some -noproc fixes
2021-03-11 20:01:10 +00:00
83fc5cc28b
Replace assert in xaiger with more useful error message
2021-03-10 22:35:06 +01:00
4e03865d5b
Add support for memory writes in processes.
2021-03-08 20:16:29 +01:00
ab76d9cec5
cxxrtl: don't assert on edge sync rules tied to a constant.
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These are commonly the result of tying an async reset to an inactive
level.
2021-03-07 14:29:30 +00:00
d1de08e38a
cxxrtl: allow `always` sync rules in debug_eval.
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These can be produced from `always @*` processes, if `-noproc`
is used.
2021-03-07 14:28:45 +00:00
9dd813374e
Merge pull request #2635 from whitequark/cxxrtl-memrd-async-addr
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cxxrtl: follow aliases to outlines when emitting $memrd.ADDR
2021-03-05 05:30:19 -08:00
06da2e0f18
Merge pull request #2634 from whitequark/cxxrtl-debug-wire-types
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cxxrtl: add pass debug flag to show assigned wire types
2021-03-05 04:57:22 -08:00
14ce8bdaa6
cxxrtl: follow aliases to outlines when emitting $memrd.ADDR.
2021-03-05 12:09:02 +00:00
8471808834
cxxrtl: add pass debug flag to show assigned wire types.
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Refs #2543 .
2021-03-05 11:58:59 +00:00
a9a873a1d2
cxxrtl: don't crash on empty designs.
2021-03-05 11:05:19 +00:00
979347999f
btor, smt2, smv: Add a hint on how to deal with funny FF types.
2021-02-25 22:04:04 +01:00
a77fa6709b
Merge pull request #2563 from whitequark/cxxrtl-msvc
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cxxrtl: do not use `->template` for non-dependent names
2021-01-26 21:55:12 +00:00
4b6e764c46
cxxrtl: do not use `->template` for non-dependent names.
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This breaks build on MSVC but not GCC/Clang.
2021-01-26 18:09:53 +00:00
c8415884d1
Improves the previous commit with a more complete coverage of the cases
2021-01-15 13:59:20 -06:00
86607d0fdc
Handle sliced bits as clock inputs ( fixes #2542 )
2021-01-14 16:36:21 -06:00
e789a00557
add buffer option to spice backend
2021-01-13 17:24:28 +01:00
Marcelina Kościelnicka
whitequark
GCHQDeveloper560
Claire Xenia Wolf
Eddie Hung
Dan Ravensloft
Iris Johnson
Pepijn de Vos