riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
1,450 Commits 114 Branches 50 Tags 34 MiB
Commit Graph

340 Commits

Author SHA1 Message Date
Clifford Wolf 523df73145 Added support for truncating of wires to wreduce pass 2014-08-05 14:47:03 +02:00
Clifford Wolf ebbbe7fc83 Added RTLIL::IdString::in(...) 2014-08-04 15:40:07 +02:00
Clifford Wolf 653edd7a2f Added query() API to ModIndex 2014-08-03 15:00:38 +02:00
Clifford Wolf 75423169c5 Added ID() macro for static IdStrings 2014-08-03 14:59:13 +02:00
Clifford Wolf bc947d4c7b Fixed a va_list corruption in logv_error() 2014-08-02 21:54:30 +02:00
Clifford Wolf b6acbc82e6 Bugfix in "techmap -extern" 2014-08-02 20:54:30 +02:00
Clifford Wolf 8e7361f128 Removed at() method from RTLIL::IdString 2014-08-02 19:08:02 +02:00
Clifford Wolf 04727c7e0f No implicit conversion from IdString to anything else 2014-08-02 18:58:40 +02:00
Clifford Wolf 768eb846c4 More bugfixes related to new RTLIL::IdString 2014-08-02 18:14:21 +02:00
Clifford Wolf 08392aad8f Limit size of log_signal buffer to 100 elements 2014-08-02 15:52:21 +02:00
Clifford Wolf e590ffc84d Improvements in new RTLIL::IdString implementation 2014-08-02 15:44:10 +02:00
Clifford Wolf 60f3dc9923 Implemented new reference counting RTLIL::IdString 2014-08-02 15:11:35 +02:00
Clifford Wolf 97ad0623df Fixed memory corruption related to id2cstr() 2014-08-02 13:34:07 +02:00
Clifford Wolf b9bd22b8c8 More cleanups related to RTLIL::IdString usage 2014-08-02 13:19:57 +02:00
Clifford Wolf 14412e6c95 Preparations for RTLIL::IdString redesign: cleanup of existing code 2014-08-02 00:45:25 +02:00
Clifford Wolf 75ffd1643c Added logfile hash to statistics footer 2014-08-01 19:43:28 +02:00
Clifford Wolf 1e224506be Added per-pass cpu usage statistics 2014-08-01 18:42:10 +02:00
Clifford Wolf d13eb7e099 Added ModIndex helper class, some changes to RTLIL::Monitor 2014-08-01 17:14:32 +02:00
Clifford Wolf 97a17d39e2 Packed SigBit::data and SigBit::offset in a union 2014-08-01 15:25:42 +02:00
Clifford Wolf 32a1cc3efd Renamed modwalker.h to modtools.h 2014-07-31 23:30:18 +02:00
Clifford Wolf cdae8abe16 Renamed port access function on RTLIL::Cell, added param access functions 2014-07-31 16:38:54 +02:00
Clifford Wolf b5a9e51b96 Added "trace" command 2014-07-31 15:02:16 +02:00
Clifford Wolf cd9407404a Added RTLIL::Monitor 2014-07-31 14:45:14 +02:00
Clifford Wolf e6d33513a5 Added module->design and cell->module, wire->module pointers 2014-07-31 14:11:39 +02:00
Clifford Wolf 1cb25c05b3 Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace 2014-07-31 13:19:47 +02:00
Clifford Wolf 6166c76831 Added "yosys -A" 2014-07-31 01:05:27 +02:00
Clifford Wolf e5c245df9d Added "yosys -Q" 2014-07-31 00:53:21 +02:00
Clifford Wolf 2541489105 Added techmap CONSTMAP feature 2014-07-30 22:04:30 +02:00
Clifford Wolf 6400ae3648 Added write_file command 2014-07-30 19:59:29 +02:00
Clifford Wolf 3f0a5746ef Using native ezSAT shift ops in satgen, fixed $shift and $shiftx SAT models 2014-07-30 18:37:17 +02:00
Clifford Wolf 45fd26b76e Added "log_dump_val_worker(char *v)" 2014-07-30 15:58:21 +02:00
Clifford Wolf a7c6b37abf Added "kernel/yosys.h" and "kernel/yosys.cc" 2014-07-30 14:10:15 +02:00
Clifford Wolf 273383692a Added "test_cell" command 2014-07-29 22:07:41 +02:00
Clifford Wolf e6df25bf74 Renamed "write_autotest" to "test_autotb" and moved to passes/tests/ 2014-07-29 21:12:50 +02:00
Clifford Wolf 03c96f9ce7 Added "techmap -map %{design-name}" 2014-07-29 16:35:13 +02:00
Clifford Wolf 397b00252d Added $shift and $shiftx cell types (needed for correct part select behavior) 2014-07-29 16:35:13 +02:00
Clifford Wolf 3c45277ee0 Added wire->upto flag for signals such as "wire [0:7] x;" 2014-07-28 12:12:13 +02:00
Clifford Wolf 7bd2d1064f Using log_assert() instead of assert() 2014-07-28 11:27:48 +02:00
Clifford Wolf d86a25f145 Added std::initializer_list<> constructor to SigSpec 2014-07-28 10:52:58 +02:00
Clifford Wolf f99495a895 Added cover() to all SigSpec constructors 2014-07-28 10:52:30 +02:00
Clifford Wolf c4bdba78cb Added proper Design->addModule interface 2014-07-27 21:12:09 +02:00
Clifford Wolf 5da343b7de Added topological sorting to techmap 2014-07-27 16:43:39 +02:00
Clifford Wolf 0c86d6106c Added SigPool::check(bit) 2014-07-27 15:38:02 +02:00
Clifford Wolf ddd31a0b66 Small improvements in PerformanceTimer API 2014-07-27 15:14:02 +02:00
Clifford Wolf d07a871d35 Improved performance of opt_const on large modules 2014-07-27 14:50:25 +02:00
Clifford Wolf 4be645860b Added RTLIL::SigSpec::remove_const() handling of packed SigSpecs 2014-07-27 14:47:48 +02:00
Clifford Wolf cbc3a46a97 Added RTLIL::SigSpecConstIterator 2014-07-27 14:47:23 +02:00
Clifford Wolf d878fcbdc7 Added log_cmd_error_expection 2014-07-27 12:05:50 +02:00
Clifford Wolf 675cb93da9 Added RTLIL::Module::wire(id) and cell(id) lookup functions 2014-07-27 11:18:31 +02:00
Clifford Wolf 0bd8fafbd2 Added RTLIL::Design::modules() 2014-07-27 11:18:30 +02:00