riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
3,511 Commits 114 Branches 50 Tags 54 MiB
Commit Graph

42 Commits

Author SHA1 Message Date
Clifford Wolf 5f1d0b1024 Add $live and $fair cell types, add support for s_eventually keyword 2017-02-25 10:36:39 +01:00
Clifford Wolf eae390ae17 Removed $predict again 2016-08-28 21:35:33 +02:00
Clifford Wolf 8537c4d206 Renamed AbstractCellEdgesDatabase::add_cell() to add_edges_from_cell() 2016-07-25 16:39:25 +02:00
Clifford Wolf b1c432af56 Improvements in CellEdgesDatabase 2016-07-24 17:21:53 +02:00
Clifford Wolf f162b858f2 Added CellEdgesDatabase API 2016-07-24 13:59:57 +02:00
Clifford Wolf d7763634b6 After reading the SV spec, using non-standard predict() instead of expect() 2016-07-21 13:34:33 +02:00
Clifford Wolf 721f1f5ecf Added basic support for $expect cells 2016-07-13 16:56:17 +02:00
Clifford Wolf 95757efb25 Improved support for $sop cells 2016-06-17 16:31:16 +02:00
Clifford Wolf 207736b4ee Import more std:: stuff into Yosys namespace 2015-10-25 19:30:49 +01:00
Clifford Wolf ddcfc99f8c Added "test_cell -noeval" 2015-09-25 17:27:18 +02:00
Clifford Wolf 0350074819 Re-created command-reference-manual.tex, copied some doc fixes to online help 2015-08-14 11:27:19 +02:00
Clifford Wolf 56d4822719 Renamed "aig" to "aigmap" 2015-06-10 07:24:26 +02:00
Clifford Wolf 85287295b2 Fixed cellaigs port extending 2015-06-10 07:16:30 +02:00
Clifford Wolf 4e6ca7760f Replaced ezDefaultSAT with ezSatPtr 2015-02-21 12:15:41 +01:00
Clifford Wolf b748622a7f Added "test_cell -muxdiv" 2014-12-25 19:22:39 +01:00
Clifford Wolf 7dece74fae Added "test_cell -w" feature 2014-12-25 17:04:13 +01:00
Clifford Wolf 41db98ba31 Fixed typo in test_cell 2014-10-18 16:52:06 +01:00
Clifford Wolf 4569a747f8 Renamed SIZE() to GetSize() because of name collision on Win32 2014-10-10 17:07:24 +02:00
Clifford Wolf f9a307a50b namespace Yosys 2014-09-27 16:17:53 +02:00
Clifford Wolf af0c8873bb Added $lcu cell type 2014-09-08 13:31:04 +02:00
Clifford Wolf d46bac3305 Added "$fa" cell type 2014-09-08 12:15:39 +02:00
Clifford Wolf 6747a7047e Added "test_cell -const" 2014-09-08 11:12:39 +02:00
Clifford Wolf 15b3c54fea Added "test_cell -nosat" 2014-09-07 17:05:41 +02:00
Clifford Wolf 9329a76818 Various bug fixes (related to $macc model testing) 2014-09-06 20:30:46 +02:00
Clifford Wolf fa64942018 Added $macc SAT model 2014-09-06 19:44:11 +02:00
Clifford Wolf b847ec8a0b Added $macc cell type 2014-09-06 15:47:46 +02:00
Clifford Wolf e1743b3bac Added "test_cell -script" 2014-09-06 11:46:07 +02:00
Clifford Wolf 8927aa6148 Removed $bu0 cell type 2014-09-04 02:07:52 +02:00
Clifford Wolf 5733f4a39d Fixed "test_cells -vlog" 2014-09-03 13:43:37 +02:00
Clifford Wolf f1869667ca Improvements in "test_cell -vlog" 2014-09-02 23:21:15 +02:00
Clifford Wolf 66bf2bb92e Added test_cell -vlog 2014-09-02 22:49:43 +02:00
Clifford Wolf acd7a99aef Added SAT testing to test_cell eval stage 2014-09-02 17:28:13 +02:00
Clifford Wolf 630befdf6d Added $alu support to test_cell 2014-09-01 16:36:04 +02:00
Clifford Wolf c7f81e4e49 Added "test_cell -simlib -v" 2014-09-01 15:37:21 +02:00
Clifford Wolf e3664066d5 Added eval testing to test_cell 2014-08-31 18:08:42 +02:00
Clifford Wolf 8649b57b6f Added $lut support in test_cell, techmap, satgen 2014-08-31 17:43:31 +02:00
Clifford Wolf 3b9157f9a6 Added "test_cell -s <seed>" 2014-08-16 19:44:31 +02:00
Clifford Wolf 13f2f36884 RIP $safe_pmux 2014-08-14 11:39:46 +02:00
Clifford Wolf cdae8abe16 Renamed port access function on RTLIL::Cell, added param access functions 2014-07-31 16:38:54 +02:00
Clifford Wolf 6ca0c569d9 Added "techmap -assert" 2014-07-31 02:21:41 +02:00
Clifford Wolf ceecf5b153 Improvements in test_cell 2014-07-30 18:49:12 +02:00
Clifford Wolf 273383692a Added "test_cell" command 2014-07-29 22:07:41 +02:00