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6600 Commits

Author SHA1 Message Date
Eddie Hung 7dca8def52 Fix issue with part of PI being 1'bx 2019-06-20 17:29:45 -07:00
Eddie Hung e63324f5ef Actually, there might not be any harm in updating sigmap... 2019-06-20 17:03:05 -07:00
Eddie Hung 9c61fb0e0c Add comment as per @cliffordwolf 2019-06-20 16:57:54 -07:00
Eddie Hung d1dadfcec8 Call opt_expr -mux_undef to get rid of 1'bx in muxes prior to abc 2019-06-20 16:45:09 -07:00
Eddie Hung 9faab38e8d mux_map to drop sign bit, and eliminate 'bx-es 2019-06-20 16:45:04 -07:00
Eddie Hung 99ff7b5c8c Merge remote-tracking branch 'origin/eddie/fix1115' into xc7mux 2019-06-20 16:08:58 -07:00
Eddie Hung 31b0dee7f3 Merge remote-tracking branch 'origin/eddie/fix1118' into xc7mux 2019-06-20 16:08:36 -07:00
Eddie Hung c20adc5263 Add test 2019-06-20 16:07:22 -07:00
Eddie Hung c27ab609fa Make genvar a signed type 2019-06-20 16:04:12 -07:00
Eddie Hung 3b8f3a93ad Add CHANGELOG entry 2019-06-20 12:45:40 -07:00
Eddie Hung d0bbf9e4d4 Extend sign extension tests 2019-06-20 12:43:59 -07:00
Eddie Hung 20119ee50e Maintain "is_unsized" state of constants 2019-06-20 12:43:39 -07:00
Eddie Hung e33cbb0dde Revert "Fix sign extension when sign is 1'bx" 
This reverts commit 0221f3e1c5.
 2019-06-20 12:40:05 -07:00
Eddie Hung 0e3e647596 Handle COs driven by 1'bx 2019-06-20 10:47:20 -07:00
Ben Widawsky 8767ec3fbd Add a few more filename rewrites 
This now allows a full pipeline to work, something such as:
yosys -p "synth_ecp5 -json ~/work/fpga/prjtrellis/examples/ecp5_evn/blinky.v"

Otherwise, you will get something along the lines of:
ERROR: Can't open output file `~/work/fpga/prjtrellis/examples/ecp5_evn/blinky.v' for writing: No such file or directory

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
 2019-06-20 10:27:59 -07:00
Eddie Hung f54edf1e78 Do not call "setundef -zero" in abc9 2019-06-20 10:22:14 -07:00
Eddie Hung efdb057c6a write_xaiger to skip POs driven by 1'bx 2019-06-20 10:21:57 -07:00
Eddie Hung cdbcd2efbd Merge remote-tracking branch 'origin/eddie/fix1115' into xc7mux 2019-06-20 10:18:10 -07:00
Eddie Hung f374e0ab7e Merge remote-tracking branch 'origin/master' into xc7mux 2019-06-20 10:18:01 -07:00
Eddie Hung b77322034c Remove leftover comment 2019-06-20 10:15:04 -07:00
Eddie Hung b98276fa61 Add test 2019-06-20 10:13:52 -07:00
Eddie Hung 0221f3e1c5 Fix sign extension when sign is 1'bx 2019-06-20 10:13:52 -07:00
Clifford Wolf 477e566e8d Fix typo, fixes #1095 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-20 15:34:52 +02:00
Clifford Wolf 06eb87bcb7 Improve shregmap help message, fixes #1113 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-20 15:23:55 +02:00
Clifford Wolf a8c85d1b4b Update some .gitignore files 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-20 14:27:57 +02:00
Clifford Wolf 2454ad99bf Refactor "opt_rmdff -sat" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-20 13:44:21 +02:00
Clifford Wolf 73bd1d59a7 Merge branch 'master' of https://github.com/bogdanvuk/yosys into clifford/ext1046 2019-06-20 13:04:04 +02:00
Clifford Wolf 11ec7b2aec Fix typo 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-20 12:23:07 +02:00
Clifford Wolf 7f1461d64b Merge branch 'towoe-unpacked_arrays' 2019-06-20 12:06:58 +02:00
Clifford Wolf 6a6dd5e057 Add proper test for SV-style arrays 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-20 12:06:07 +02:00
Clifford Wolf 2428fb7dc2 Merge branch 'unpacked_arrays' of https://github.com/towoe/yosys-sv into towoe-unpacked_arrays 2019-06-20 12:03:00 +02:00
Eddie Hung 3b1e5264d8
Merge pull request #1111 from acw1251/help_summary_fixes 
Fixed the help summary line for a few commands
 2019-06-19 15:30:50 -07:00
acw1251 ce29ede801 Fixed small typo in ice40_unlut help summary 2019-06-19 16:39:46 -04:00
acw1251 0d888ee7ed Fixed the help summary line for a few commands 2019-06-19 15:27:04 -04:00
Eddie Hung 96ade54993 Fix bug in #1078, add entry to CHANGELOG 2019-06-19 09:51:11 -07:00
Eddie Hung 4e8f0fbce8 Merge branch 'xaig' into xc7mux 2019-06-19 09:20:31 -07:00
Clifford Wolf 8395f837c3
Merge pull request #1109 from YosysHQ/clifford/fix1106 
Add "read_verilog -pwires" feature
 2019-06-19 17:25:39 +02:00
Clifford Wolf ec4565009a Add "read_verilog -pwires" feature, closes #1106 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-19 14:38:50 +02:00
Clifford Wolf 5a1f1caa44
Merge pull request #1105 from YosysHQ/clifford/fixlogicinit 
Improve handling of initial/default values
 2019-06-19 13:53:07 +02:00
Tobias Wölfel 8b8af10f5e Unpacked array declaration using size 
Allows fixed-sized array dimension specified by a single number.

This commit is based on the work from PeterCrozier
https://github.com/YosysHQ/yosys/pull/560.
But is split out of the original work.
 2019-06-19 12:47:48 +02:00
Clifford Wolf c330379870 Make tests/aiger less chatty 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-19 12:20:35 +02:00
Clifford Wolf fa5fc3f6af Add defvalue test, minor autotest fixes for .sv files 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-19 12:12:08 +02:00
Clifford Wolf 3da5288ce0 Use input default values in hierarchy pass 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-19 11:49:20 +02:00
Clifford Wolf 8d0cd529c9 Add defaultvalue attribute 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-19 11:37:11 +02:00
Clifford Wolf 6d64e242ba Fix handling of "logic" variables with initial value 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-19 11:25:11 +02:00
Clifford Wolf b3441935b1
Merge pull request #1100 from bwidawsk/home 
Support ~ in filename parsing
 2019-06-19 10:52:59 +02:00
Clifford Wolf eb3b9fb24a
Merge pull request #1104 from whitequark/case-semantics 
Clarify switch/case semantics in RTLIL
 2019-06-19 10:50:32 +02:00
whitequark addf01d45d Explain exact semantics of switch and case rules in the manual. 2019-06-19 05:22:40 +00:00
whitequark df6576edc8 In RTLIL::Module::check(), check process invariants. 2019-06-19 05:22:13 +00:00
Ben Widawsky 4a18e19fb8 Support filename rewrite in backends 
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
 2019-06-18 14:39:52 -07:00