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Add CHANGELOG entry

This commit is contained in:
Eddie Hung 2019-06-20 12:45:40 -07:00
parent d0bbf9e4d4
commit 3b8f3a93ad
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CHANGELOG
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@ -19,6 +19,7 @@ Yosys 0.8 .. Yosys 0.8-dev
- Added "read_aiger" frontend
- Extended "muxcover -mux{4,8,16}=<cost>"
- "synth_xilinx" to now infer hard shift registers, using new "shregmap -tech xilinx"
- Fixed sign extension of unsized constants with 'bx and 'bz MSB
Yosys 0.7 .. Yosys 0.8
@ -32,7 +33,7 @@ Yosys 0.7 .. Yosys 0.8
- Added "write_verilog -decimal"
- Added "scc -set_attr"
- Added "verilog_defines" command
- Remeber defines from one read_verilog to next
- Remember defines from one read_verilog to next
- Added support for hierarchical defparam
- Added FIRRTL back-end
- Improved ABC default scripts