riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Do not call "setundef -zero" in abc9

This commit is contained in:
Eddie Hung 2019-06-20 10:22:14 -07:00
parent efdb057c6a
commit f54edf1e78
1 changed files with 2 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
passes/techmap/abc9.cc
View File

@ -380,9 +380,6 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
RTLIL::Selection& sel = design->selection_stack.back();
sel.select(module);
// Behave as for "abc" where BLIF writer implicitly outputs all undef as zero
Pass::call(design, "setundef -zero");
Pass::call(design, "aigmap");
handle_loops(design);
@ -406,7 +403,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
reader.parse_xaiger();
}
ifs.close();
Pass::call(design, stringf("write_verilog -noexpr -norename %s/%s", tempdir_name.c_str(), "input.v"));
Pass::call(design, stringf("write_verilog -noexpr -norename"));
design->remove(design->module("$__abc9__"));
#endif
@ -479,7 +476,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
ifs.close();
#if 0
Pass::call(design, stringf("write_verilog -noexpr -norename %s/%s", tempdir_name.c_str(), "output.v"));
Pass::call(design, stringf("write_verilog -noexpr -norename"));
#endif
log_header(design, "Re-integrating ABC9 results.\n");