mirror of https://github.com/YosysHQ/yosys.git
write_xaiger to skip POs driven by 1'bx
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@ -152,9 +152,13 @@ struct XAigerWriter
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}
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if (wire->port_output || keep) {
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if (bit != wirebit)
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alias_map[wirebit] = bit;
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output_bits.insert(wirebit);
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if (bit != RTLIL::Sx) {
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if (bit != wirebit)
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alias_map[wirebit] = bit;
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output_bits.insert(wirebit);
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}
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else
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log_debug("Skipping PO '%s' driven by 1'bx\n", log_signal(wirebit));
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}
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}
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}
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