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8057 Commits

Author SHA1 Message Date
Eddie Hung 946d5854c0 Drop keep=0 attributes on SB_CARRY 2019-12-06 17:27:47 -08:00
Eddie Hung 91467938c4 Stray newline 2019-12-06 17:08:19 -08:00
Eddie Hung f2ac36de4a write_xaiger to inst each cell type once, do not call techmap/aigmap 2019-12-06 17:06:10 -08:00
Eddie Hung 98c9ea605b techmap/aigmap of whiteboxes to occur before abc9 instead of in write_xaiger 2019-12-06 17:05:02 -08:00
Jan Kowalewski dcb30b5f4a tests: arch: xilinx: Change order of arguments in macc.sh 2019-12-06 09:15:49 +01:00
Clifford Wolf 7dece7955e
Merge pull request #1551 from whitequark/manual-cell-operands 
Clarify semantics of comb cells, in particular shifts
 2019-12-05 08:24:24 -08:00
Eddie Hung a7e0cca480 Merge SB_CARRY+SB_LUT4's attributes when creating $__ICE40_CARRY_WRAPPER 2019-12-05 07:01:18 -08:00
Eddie Hung d8fbf88980 Add WIP test for unwrapping $__ICE40_CARRY_WRAPPER 2019-12-05 07:01:02 -08:00
whitequark e97e33d00d kernel: require \B_SIGNED=0 on $shl, $sshl, $shr, $sshr. 
Before this commit, these cells would accept any \B_SIGNED and in
case of \B_SIGNED=1, would still treat the \B input as unsigned.

Also fix the Verilog frontend to never emit such constructs.
 2019-12-04 11:59:36 +00:00
whitequark ec4c9267b3 manual: document behavior of many comb cells more precisely. 2019-12-04 11:32:14 +00:00
Marcin Kościelnicki fcce94010f
xilinx: Add tristate buffer mapping. (#1528) 
Fixes #1225.
 2019-12-04 09:44:00 +01:00
Marcin Kościelnicki 2abe38e73e
iopadmap: Refactor and fix tristate buffer mapping. (#1527) 
The previous code for rerouting wires when inserting tristate buffers
was overcomplicated and didn't handle all cases correctly (in
particular, only cell connections were rewired — internal connections
were not).
 2019-12-04 08:44:08 +01:00
Marcin Kościelnicki 10014e2643
xilinx: Add models for LUTRAM cells. (#1537) 2019-12-04 06:31:09 +01:00
Eddie Hung 67f1ce2d43 Check SB_CARRY name also preserved 2019-12-03 14:51:39 -08:00
Eddie Hung ed3f359175 $__ICE40_CARRY_WRAPPER to use _TECHMAP_REPLACE_ for SB_CARRY to preserve 
name and attr
 2019-12-03 14:49:10 -08:00
Eddie Hung 1ea9ce0ad7 ice40_opt to ignore (* keep *) -ed cells 2019-12-03 14:48:39 -08:00
Eddie Hung 5897b918b3 ice40_wrapcarry to preserve SB_CARRY's attributes 2019-12-03 14:48:11 -08:00
Eddie Hung 8de17877d4 Add testcase 2019-12-03 14:48:00 -08:00
Clifford Wolf 2ec6d832dc
Merge pull request #1524 from pepijndevos/gowindffinit 
Gowin: add and test DFF init values
 2019-12-03 08:43:18 -08:00
Pepijn de Vos a7d34a7cb5 update test 2019-12-03 16:56:15 +01:00
Pepijn de Vos a3b25b4af8 Use -match-init to not synth contradicting init values 2019-12-03 15:12:25 +01:00
David Shah 7f35b2ff62
Merge pull request #1542 from YosysHQ/dave/abc9-loop-fix 
abc9: Fix breaking of SCCs
 2019-12-02 10:20:21 +00:00
Clifford Wolf cacf870d85
Merge pull request #1539 from YosysHQ/mwk/ilang-bounds-check 
read_ilang: do bounds checking on bit indices
 2019-12-01 16:30:48 -08:00
David Shah e9ce4e658b abc9: Fix breaking of SCCs 
Signed-off-by: David Shah <dave@ds0.me>
 2019-12-01 20:44:56 +00:00
Miodrag Milanović 5f4c35c753
Merge pull request #1540 from YosysHQ/mwk/xilinx-bufpll 
xilinx: Add missing blackbox cell for BUFPLL.
 2019-11-29 17:33:41 +01:00
Marcin Kościelnicki 2badaa9adb xilinx: Add missing blackbox cell for BUFPLL. 2019-11-29 16:56:27 +01:00
Eddie Hung 419ca5c207 Revert "Fold loop" 
This reverts commit a30d5e1cc3.
 2019-11-27 21:55:56 -08:00
Marcin Kościelnicki 0ce22cea46 read_ilang: do bounds checking on bit indices 2019-11-27 22:24:39 +01:00
Diego H 3a5a65829c Adjusting Vivado's BRAM min bits threshold for RAMB18E1 2019-11-27 12:05:04 -06:00
Eddie Hung 6464dc35ec
Merge pull request #1536 from YosysHQ/eddie/xilinx_dsp_muladd 
xilinx_dsp: consider sign and zero-extension when packing post-multiplier adder
 2019-11-27 08:00:22 -08:00
Clifford Wolf 41e0ddf4f4
Merge pull request #1501 from YosysHQ/dave/mem_copy_attr 
memory_collect: Copy attr from RTLIL::Memory to  cell
 2019-11-27 11:25:23 +01:00
Clifford Wolf f43c0bd8ba
Merge pull request #1534 from YosysHQ/mwk/opt_share-fix 
opt_share: Fix handling of fine cells.
 2019-11-27 11:23:16 +01:00
Eddie Hung 95053d9010
Merge pull request #1535 from YosysHQ/eddie/write_xaiger_improve 
write_xaiger improvements
 2019-11-27 01:04:29 -08:00
Eddie Hung de3476cc23 No need for -abc9 2019-11-26 23:08:14 -08:00
Marcin Kościelnicki fdcbda195b opt_share: Fix handling of fine cells. 
Fixes #1525.
 2019-11-27 08:01:07 +01:00
Eddie Hung 5e67df38ed latch -> box 2019-11-26 22:59:05 -08:00
Eddie Hung 4a0198128e Add citation 2019-11-26 22:51:16 -08:00
Eddie Hung 2105ae176a Check for either sign or zero extension for postAdd packing 2019-11-26 22:51:00 -08:00
Eddie Hung 15042eaf57 Remove notes 2019-11-26 22:41:35 -08:00
Eddie Hung a30d5e1cc3 Fold loop 2019-11-26 21:57:50 -08:00
Eddie Hung 68717dd03b Do not sigmap keep bits inside write_xaiger 2019-11-26 21:57:50 -08:00
Eddie Hung 7136cee6b4 xaiger: do not promote output wires 2019-11-26 21:55:37 -08:00
Eddie Hung 222e199b73 Add testcase derived from fastfir_dynamictaps benchmark 2019-11-26 21:26:30 -08:00
Marcin Kościelnicki 0466c48533 xilinx: Add simulation models for IOBUF and OBUFT. 2019-11-26 08:15:20 +01:00
Marcin Kościelnicki 6cdea425b8 clkbufmap: Add support for inverters in clock path. 2019-11-25 20:40:39 +01:00
Marcin Kościelnicki 7562e7304e xilinx: Use INV instead of LUT1 when applicable 2019-11-25 20:40:39 +01:00
Pepijn de Vos 72d03dc910 attempt to fix formatting 2019-11-25 14:50:34 +01:00
Pepijn de Vos 6c79abbf5a gowin: add and test dff init values 2019-11-25 14:33:21 +01:00
Eddie Hung db2268703f
Merge pull request #1520 from pietrmar/fix-1463 
coolrunner2: remove spurious log_pop() call, fixes #1463
 2019-11-22 22:45:40 -08:00
Martin Pietryka 97b22413e5 coolrunner2: remove spurious log_pop() call, fixes #1463 
This was causing a segmentation fault because there is no accompanying
log_push() call so header_count.size() became -1.

Signed-off-by: Martin Pietryka <martin@pietryka.at>
 2019-11-23 06:21:40 +01:00