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1,860 Commits 86 Branches 51 Tags 35 MiB
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481 Commits

Author SHA1 Message Date
Clifford Wolf 3be5fa053f Fixed RTLIL::SigSpec::parse() for out-of-range bit- and part-selects 2014-10-16 00:54:14 +02:00
Clifford Wolf 82ed814fa1 Replaced log_assert() do { ... } while (0) hack with a static inline function 2014-10-15 20:36:32 +02:00
Clifford Wolf 2355ddf75d Fixed gcc warning 2014-10-15 02:48:51 +02:00
Clifford Wolf 3445a933a5 Fixed MXE build 2014-10-15 02:43:50 +02:00
Clifford Wolf 1fc6208ec0 Check for _YOSYS_ in yosys.h 2014-10-15 01:18:31 +02:00
Clifford Wolf c3e9922b5d Replaced readsome() with read() and gcount() 2014-10-15 01:12:53 +02:00
Clifford Wolf cf85aab62f A few indent fixes 2014-10-15 01:05:08 +02:00
William Speirs 9cb2303799 Made iterators extend std::iterator and added == operator 2014-10-15 00:56:37 +02:00
Clifford Wolf 069521e2d5 Define empty __attribute__ macro for non-gcc, non-clang compilers 2014-10-15 00:56:04 +02:00
William Speirs 0352dbfd65 Fixed log so it will compile under Visual Studio 
- Included an implementation of gettimeofday
 2014-10-15 00:48:59 +02:00
Clifford Wolf 0913e968f5 More win32/abc fixes 2014-10-12 14:48:19 +02:00
Clifford Wolf 1a7684be24 Various small fixes for non-win32 builds 2014-10-12 12:18:38 +02:00
Clifford Wolf 0b9282a779 Added make_temp_{file,dir}() and remove_directory() APIs 2014-10-12 12:11:57 +02:00
Clifford Wolf b1596bc0e7 Added run_command() api to replace system() and popen() 2014-10-12 10:57:15 +02:00
Clifford Wolf 0dc249ccd7 Shrinked the copyright banner by 1 character 2014-10-11 11:59:35 +02:00
Clifford Wolf 8263f6a74a Fixed win32 troubles with f.readsome() 2014-10-11 11:36:22 +02:00
Clifford Wolf 568fee5e74 Added proc_self_dirname() for win32 2014-10-11 11:08:52 +02:00
Clifford Wolf 53349fb634 Fixed ifdefs for plugin unloading 2014-10-11 10:57:46 +02:00
Clifford Wolf df537a216b Using next_token() to parse commands 2014-10-10 18:53:03 +02:00
Clifford Wolf 20d85f20db Fixed next_token() 2014-10-10 18:38:40 +02:00
Clifford Wolf 2c683102be Added next_token() function (strtok() replacement) 2014-10-10 18:33:55 +02:00
Clifford Wolf 986bcc13cb Various win32 build fixes in yosys.cc 2014-10-10 18:20:17 +02:00
Clifford Wolf ee5165c6e4 Moved patmatch() to yosys.cc 2014-10-10 18:20:17 +02:00
Clifford Wolf 774933a0d8 Replaced fnmatch() with patmatch() 2014-10-10 18:02:17 +02:00
Clifford Wolf bbd808072b Added format __attribute__ to stringf() 2014-10-10 17:22:08 +02:00
Clifford Wolf 7cb0d3aa1a Renamed TRUE/FALSE to CONST_TRUE/CONST_FALSE because of name collision on Win32 2014-10-10 17:07:24 +02:00
Clifford Wolf 4569a747f8 Renamed SIZE() to GetSize() because of name collision on Win32 2014-10-10 17:07:24 +02:00
Clifford Wolf c7f5aab625 Replaced "#ifdef WIN32" with "#ifdef _WIN32" 2014-10-09 17:00:54 +02:00
Clifford Wolf fea11f0fa4 Added API for generic cell cost calculations 2014-10-09 13:59:26 +02:00
Clifford Wolf d3405c15bf No rusage on win32 2014-10-09 10:51:24 +02:00
Clifford Wolf 56c1d43408 satgen import sigbit api 2014-10-03 18:51:50 +02:00
Clifford Wolf 3e4b0cac8d added resource sharing of $macc cells 2014-10-03 12:58:40 +02:00
Clifford Wolf c3e779a65f Added $_BUF_ cell type 2014-10-03 10:12:28 +02:00
Clifford Wolf 0b8cfbc6fd Added support for "keep" on modules 2014-09-29 12:51:54 +02:00
Clifford Wolf f9a307a50b namespace Yosys 2014-09-27 16:17:53 +02:00
Clifford Wolf edf11c635a Assert on new logic loops in "share" pass 2014-09-21 12:57:33 +02:00
Clifford Wolf 00964f2f61 Initialize RTLIL::Const from std::vector<bool> 2014-09-19 15:50:55 +02:00
Clifford Wolf fa96cf4a16 Added new CodingReadme file (replaces CodingStyle and CHECKLISTS) 2014-09-16 11:26:44 +02:00
Clifford Wolf b470c480e9 Added the obvious optimizations to alumacc $macc generator 2014-09-15 12:22:03 +02:00
Clifford Wolf 2442eb3832 Fixed monitor notifications for removed cell 2014-09-14 17:04:39 +02:00
Clifford Wolf 7815f81c32 Added "synth" command 2014-09-14 16:09:06 +02:00
Clifford Wolf fcb46138ce Simplified $fa undef model 2014-09-08 16:59:39 +02:00
Clifford Wolf af0c8873bb Added $lcu cell type 2014-09-08 13:31:04 +02:00
Clifford Wolf d46bac3305 Added "$fa" cell type 2014-09-08 12:15:39 +02:00
Clifford Wolf 98e6463ca7 Added $macc eval model 2014-09-06 19:44:28 +02:00
Clifford Wolf fa64942018 Added $macc SAT model 2014-09-06 19:44:11 +02:00
Clifford Wolf b847ec8a0b Added $macc cell type 2014-09-06 15:47:46 +02:00
Ruben Undheim 79cbf9067c Corrected spelling mistakes found by lintian 2014-09-06 08:47:06 +02:00
Clifford Wolf 8927aa6148 Removed $bu0 cell type 2014-09-04 02:07:52 +02:00
Clifford Wolf b9cb483f3e Using $pos models for $bu0 2014-09-03 21:20:59 +02:00
Clifford Wolf 50ac284823 Fixes in $alu SAT- and eval-models 2014-09-03 13:39:46 +02:00
Clifford Wolf da360771a1 Create a default selection stack in RTLIL::Design::Design() 2014-09-02 22:49:24 +02:00
Clifford Wolf c38283dbd0 Small bug fixes in $not, $neg, and $shiftx models 2014-09-02 17:48:41 +02:00
Clifford Wolf 2fcf66b91d Added ConstEval model for $alu cells 2014-09-01 16:35:46 +02:00
Clifford Wolf bae09dca2b Added SAT model for $alu cells 2014-09-01 16:35:25 +02:00
Clifford Wolf e07698818d Using std::vector<RTLIL::State> instead of RTLIL::Const for RTLIL::SigChunk::data 2014-09-01 11:36:02 +02:00
Clifford Wolf 83ec3fa204 Fixed return size of const_*() eval functions 2014-08-31 18:08:26 +02:00
Clifford Wolf be44157c0f Added RTLIL::Const::size() 2014-08-31 18:07:48 +02:00
Clifford Wolf a1c7d4a8e2 Added eval model for $lut cells 2014-08-31 17:43:31 +02:00
Clifford Wolf 0b6769af3f Typo fixes in cell->*Param() API 2014-08-31 17:43:31 +02:00
Clifford Wolf 8649b57b6f Added $lut support in test_cell, techmap, satgen 2014-08-31 17:43:31 +02:00
Clifford Wolf 2a1b08aeb3 Added design->scratchpad 2014-08-30 19:37:12 +02:00
Clifford Wolf 4724d94fbc Added $alu cell type 2014-08-30 18:59:05 +02:00
Clifford Wolf dfbd7dd15a Fixed module->addPmux() 2014-08-30 18:17:22 +02:00
Clifford Wolf eda603105e Added is_signed argument to SigSpec.as_int() and Const.as_int() 2014-08-24 15:14:00 +02:00
Clifford Wolf 58367cd87a Removed compatbility.{h,cc}: Not using open_memstream/fmemopen anymore 2014-08-23 15:14:58 +02:00
Clifford Wolf 19cff41eb4 Changed frontend-api from FILE to std::istream 2014-08-23 15:03:55 +02:00
Clifford Wolf 5dce303a2a Changed backend-api from FILE to std::ostream 2014-08-23 13:54:21 +02:00
Clifford Wolf 98442e019d Added emscripten (emcc) support to build system and some build fixes 2014-08-22 16:20:22 +02:00
Clifford Wolf a3494fa9ed Added "plugin" command 2014-08-22 14:00:11 +02:00
Clifford Wolf b37d70dfd7 Added mod->addGate() methods for new gate types 2014-08-19 14:26:54 +02:00
Clifford Wolf aa7a3ed83f Fixed proc_{self,share}_dirname error handling 2014-08-17 02:25:59 +02:00
Clifford Wolf f3326a6421 Improved sig.remove2() performance 2014-08-17 02:16:56 +02:00
Clifford Wolf 9bacc0b54c Added stackmap<> container 2014-08-17 00:56:47 +02:00
Clifford Wolf 410d043dd8 Renamed toposort.h to utils.h 2014-08-17 00:55:35 +02:00
Clifford Wolf 7f734ecc09 Added module->uniquify() 2014-08-16 23:50:36 +02:00
Clifford Wolf 47c2637a96 Added additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $_OAI4_ 2014-08-16 18:29:39 +02:00
Clifford Wolf 56a30cf42c Added CellTypes::cell_evaluable() 2014-08-16 16:17:07 +02:00
Clifford Wolf dbdf89c705 Added log_spacer() 2014-08-16 15:34:00 +02:00
Clifford Wolf b64b38eea2 Renamed $lut ports to follow A-Y naming scheme 2014-08-15 14:18:40 +02:00
Clifford Wolf f092b50148 Renamed $_INV_ cell type to $_NOT_ 2014-08-15 14:11:40 +02:00
Clifford Wolf ca87116449 More idstring sort_by_* helpers and fixed tpl ordering in techmap 2014-08-15 02:40:46 +02:00
Clifford Wolf 8ff71b5ae5 Added Frontend "+/" filename syntax for files from proc_share_dir 2014-08-15 02:08:02 +02:00
Clifford Wolf 978a933b6a Added RTLIL::SigSpec::to_sigbit_map() 2014-08-14 23:14:47 +02:00
Clifford Wolf 2f44d8ccf8 Added sig.{replace,remove,extract} variants for std::{map,set} pattern 2014-08-14 22:32:18 +02:00
Clifford Wolf 1bf7a18fec Added module->ports 2014-08-14 16:22:52 +02:00
Clifford Wolf 746aac540b Refactoring of CellType class 2014-08-14 15:46:51 +02:00
Clifford Wolf 13f2f36884 RIP $safe_pmux 2014-08-14 11:39:46 +02:00
Clifford Wolf e5ac8fdf2b Fixed SigBit(RTLIL::Wire *wire) constructor 2014-08-12 15:39:48 +02:00
Clifford Wolf 5215723c64 Another build fix by americanrouter (via reddit) 2014-08-11 15:55:41 +02:00
Clifford Wolf 0b8b8d41eb Fixed build with gcc-4.6 2014-08-07 22:37:01 +02:00
Clifford Wolf 523df73145 Added support for truncating of wires to wreduce pass 2014-08-05 14:47:03 +02:00
Clifford Wolf ebbbe7fc83 Added RTLIL::IdString::in(...) 2014-08-04 15:40:07 +02:00
Clifford Wolf 653edd7a2f Added query() API to ModIndex 2014-08-03 15:00:38 +02:00
Clifford Wolf 75423169c5 Added ID() macro for static IdStrings 2014-08-03 14:59:13 +02:00
Clifford Wolf bc947d4c7b Fixed a va_list corruption in logv_error() 2014-08-02 21:54:30 +02:00
Clifford Wolf b6acbc82e6 Bugfix in "techmap -extern" 2014-08-02 20:54:30 +02:00
Clifford Wolf 8e7361f128 Removed at() method from RTLIL::IdString 2014-08-02 19:08:02 +02:00
Clifford Wolf 04727c7e0f No implicit conversion from IdString to anything else 2014-08-02 18:58:40 +02:00
Clifford Wolf 768eb846c4 More bugfixes related to new RTLIL::IdString 2014-08-02 18:14:21 +02:00