mirror of https://github.com/YosysHQ/yosys.git
satgen import sigbit api
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@ -38,6 +38,7 @@ struct SatGen
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std::string prefix;
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SigPool initial_state;
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std::map<std::string, RTLIL::SigSpec> asserts_a, asserts_en;
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std::map<std::string, std::map<RTLIL::SigBit, int>> imported_signals;
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bool ignore_div_by_zero;
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bool model_undef;
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@ -52,7 +53,7 @@ struct SatGen
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this->prefix = prefix;
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}
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std::vector<int> importSigSpecWorker(RTLIL::SigSpec &sig, std::string &pf, bool undef_mode, bool dup_undef)
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std::vector<int> importSigSpecWorker(RTLIL::SigSpec sig, std::string &pf, bool undef_mode, bool dup_undef)
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{
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log_assert(!undef_mode || model_undef);
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sigmap->apply(sig);
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@ -69,6 +70,7 @@ struct SatGen
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} else {
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std::string name = pf + stringf(bit.wire->width == 1 ? "%s" : "%s [%d]", RTLIL::id2cstr(bit.wire->name), bit.offset);
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vec.push_back(ez->frozen_literal(name));
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imported_signals[pf][bit] = vec.back();
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}
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return vec;
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}
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@ -94,6 +96,20 @@ struct SatGen
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return importSigSpecWorker(sig, pf, true, false);
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}
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int importSigBit(RTLIL::SigBit bit, int timestep = -1)
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{
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log_assert(timestep != 0);
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std::string pf = prefix + (timestep == -1 ? "" : stringf("@%d:", timestep));
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return importSigSpecWorker(bit, pf, false, false).front();
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}
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bool importedSigBit(RTLIL::SigBit bit, int timestep = -1)
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{
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log_assert(timestep != 0);
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std::string pf = prefix + (timestep == -1 ? "" : stringf("@%d:", timestep));
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return imported_signals[pf].count(bit);
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}
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void getAsserts(RTLIL::SigSpec &sig_a, RTLIL::SigSpec &sig_en, int timestep = -1)
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{
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std::string pf = prefix + (timestep == -1 ? "" : stringf("@%d:", timestep));
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