mirror of https://github.com/YosysHQ/yosys.git
Added $macc eval model
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parent
fa64942018
commit
98e6463ca7
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@ -23,6 +23,7 @@
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#include "kernel/rtlil.h"
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#include "kernel/sigtools.h"
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#include "kernel/celltypes.h"
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#include "kernel/macc.h"
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struct ConstEval
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{
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@ -210,6 +211,27 @@ struct ConstEval
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}
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}
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}
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else if (cell->type == "$macc")
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{
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Macc macc;
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macc.from_cell(cell);
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if (!eval(macc.bit_ports, undef, cell))
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return false;
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for (auto &port : macc.ports) {
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if (!eval(port.in_a, undef, cell))
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return false;
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if (!eval(port.in_b, undef, cell))
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return false;
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}
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RTLIL::Const result(0, SIZE(cell->getPort("\\Y")));
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if (!macc.eval(result))
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log_abort();
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set(cell->getPort("\\Y"), result);
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}
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else
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{
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RTLIL::SigSpec sig_c, sig_d;
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