a31c8a82be
intel_alm: preliminary Arria V support
2021-11-25 17:20:36 +01:00
cb41209095
synth_gatemate Revert cascade A/B port mixup
2021-11-13 21:53:25 +01:00
decdc743db
synth_gatemate: Remove iob_map invokation
2021-11-13 21:53:25 +01:00
0d871b6c49
synth_gatemate: Add block RAM cascade support
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* add simulation model for block RAM cascade in 40K mode
* limit 20K_SDP and 40K_SDP to 40 and 80 bits (the only useful configurations)
2021-11-13 21:53:25 +01:00
285ec0547b
synth_gatemate: Remove obsolete iob_map
2021-11-13 21:53:25 +01:00
81964d6d6f
synth_gatemate: Update pass
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* remove `write_edif` and `write_blif` options
* remove redundant `abc` call before muxcover
* update style
2021-11-13 21:53:25 +01:00
74aee88e81
synth_gatemate: Remove specify blocks
2021-11-13 21:53:25 +01:00
05f24adca9
synth_gatemate: Remove gatemate_bramopt pass
2021-11-13 21:53:25 +01:00
4bee908ae8
synth_gatemate: Revise block RAM read modes and initialization
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* enable mixed read-width / write-width ports in SDP mode
* fix NO_CHANGE and WRITE_THROUGH behavior during read access
* remove redundant zero-initialization
* set A/B_WE bit during map (gatemate_bramopt pass could be removed later)
* differentiate "upper" and "lower" initialization for cascade mode
2021-11-13 21:53:25 +01:00
3f4ccdf2f5
synth_gatemate: Remove unsupported FF initialization
2021-11-13 21:53:25 +01:00
d592bd93b8
synth_gatemate: Rename multiplier factor parameters
2021-11-13 21:53:25 +01:00
6825de6343
synth_gatemate: Registers are uninitialized
2021-11-13 21:53:25 +01:00
0a72952d5f
synth_gatemate: Apply review remarks
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* remove unused techmap models in `map_regs.v`
* replace RAM initilization loops with 320-bit-writes
* add script to test targets in top-level Makefile
* remove `MAXWIDTH` parameter and treat both vector widths individually in `mult_map.v`
* iterate over all modules in `gatemate_bramopt` pass
2021-11-13 21:53:25 +01:00
cfcc38582a
synth_gatemate: Apply review remarks
2021-11-13 21:53:25 +01:00
240d289fff
synth_gatemate: Initial implementation
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Signed-off-by: Patrick Urban <patrick.urban@web.de>
2021-11-13 21:53:25 +01:00
15b0d717ed
iopadmap: Add native support for negative-polarity output enable.
2021-11-09 15:40:16 +01:00
4bf8deacbb
synth_gowin: move splitnets to after iopadmap ( #2435 )
2021-11-07 18:00:18 +01:00
a3eec687e0
Remove noalu from synth_gowin json output as Apicula now supports it
2021-11-07 03:04:21 +01:00
0c7461fe5e
gowin: widelut support ( #3042 )
2021-11-06 16:09:30 +01:00
e14302a3ea
ecp5: Add support for mapping aldff.
2021-10-27 16:18:05 +02:00
fe9689c136
Fixed Verific parser error in ice40 cell library
...
non-net output port 'Q' cannot be initialized at declaration in SystemVerilog mode
2021-10-19 12:33:18 +02:00
6e78a80ff9
CycloneV: Add (passthrough) support for cyclonev_oscillator
2021-10-17 20:00:03 +02:00
6253d4ec9e
CycloneV: Add (passthrough) support for cyclonev_hps_interface_mpu_general_purpose
2021-10-17 10:39:13 +02:00
e7d89e653c
Hook up $aldff support in various passes.
2021-10-02 21:01:21 +02:00
ec2b5548fe
Add $aldff and $aldffe: flip-flops with async load.
2021-10-02 18:12:52 +02:00
f03e2c30aa
abc9: replace cell type/parameters if derived type already processed ( #2991 )
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* Add close bracket
* Add testcase
* Replace cell type/param if in unmap_design
* Improve abc9_box error message too
* Update comment as per review
2021-09-09 10:05:55 -07:00
6de500ec08
[ECP5] fix wrong link for syn_* attributes description ( #2984 )
2021-08-29 11:45:23 +02:00
dfc453b246
Add DLLDELD
2021-08-22 18:48:44 +02:00
c2d358484f
Gowin: deal with active-low tristate ( #2971 )
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* deal with active-low tristate
* remove empty port
* update sim models
* add expected lut1 to tests
2021-08-20 21:21:06 +02:00
3806b07303
ice40: Fix typo in SB_CARRY specify for LP/UltraPlus
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Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2021-08-17 14:33:30 +02:00
fd79217763
Add v2 memory cells.
2021-08-11 13:34:10 +02:00
cfddef5d7d
Fixes xc7 BRAM36s
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UG473 from Xilinx states that 15 bit should always be set if RAMB isn't in cascade mode.
Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
2021-07-30 16:17:22 +02:00
54e75129e5
opt_lut: Allow more than one -dlogic per cell type.
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Fixes #2061 .
2021-07-29 17:30:07 +02:00
19720b970d
memory: Introduce $meminit_v2 cell, with EN input.
2021-07-28 23:18:38 +02:00
726fabd65e
ice40: Fix LUT input indices in opt_lut -dlogic (again).
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Fixes #2061 .
2021-07-10 21:30:01 +02:00
2b8f1633ce
ecp5: Add DCSC blackbox
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-07-06 14:07:20 +01:00
06b99950ed
Fix icestorm links
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Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2021-06-09 12:39:12 +02:00
0ada13cbe2
Use HTTPS for website links, gatecat email
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git ls-tree -r --name-only HEAD | xargs sed -i -rf ~/fixemails.sed
s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi;
s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi;
s/((David)\s+)+(Shah|gatecat)\s+<(dave|david|gatecat)@(symbioticeda.com|yosyshq.com|ds0.me)>/gatecat <gatecat@ds0.me>/gi;
s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi;
s,https?://www.clifford.at/yosys/|http://yosyshq.net/yosys/,https://yosyshq.net/yosys/,g ;
2021-06-09 12:16:56 +02:00
92e705cb51
Fix files with CRLF line endings
2021-06-09 12:16:33 +02:00
72787f52fc
Fixing old e-mail addresses and deadnames
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s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi;
s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi;
s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi;
s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi;
s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g ;
2021-06-08 00:39:36 +02:00
34a08750fa
intel_alm: Fix illegal carry chains
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-05-15 22:37:06 +01:00
eb106732d9
intel_alm: Add global buffer insertion
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-05-15 22:37:06 +01:00
5dba138c87
intel_alm: Add IO buffer insertion
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-05-15 22:37:06 +01:00
9e02786d39
Add missing parameters for MULT18X18D and ALU54B to ECP5 techlib.
2021-05-12 10:04:34 +01:00
67d6f3973b
Fix use of blif name in synth_xilinx command
2021-04-27 02:29:52 -07:00
46d3f03d27
Add default assignments to other SB_* simulation models
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Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2021-04-20 18:52:36 +02:00
8aee80040d
Add default assignments to SB_LUT4
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Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2021-04-20 12:46:21 +02:00
dce037a62c
quicklogic: ABC9 synthesis
2021-04-17 20:54:58 +02:00
a58571d0fe
sf2: fix name of AND modules
2021-04-09 16:46:05 +02:00
55dc5a4e4f
abc9: fix SCC issues ( #2694 )
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* xilinx: add SCC test for DSP48E1
* xilinx: Gate DSP48E1 being a whitebox behind ALLOW_WHITEBOX_DSP48E1
Have a test that checks it works through ABC9 when enabled
* abc9 to break SCCs using $__ABC9_SCC_BREAKER module
* Add test
* abc9_ops: remove refs to (* abc9_keep *) on wires
* abc9_ops: do not bypass cells in an SCC
* Add myself to CODEOWNERS for abc9*
* Fix compile
* abc9_ops: run -prep_hier before scc
* Fix tests
* Remove bug reference pending fix
* abc9: fix for -prep_hier -dff
* xaiger: restore PI handling
* abc9_ops: -prep_xaiger sigmap
* abc9_ops: -mark_scc -> -break_scc
* abc9: eliminate hard-coded abc9.box from tests
Also tidy up
* Address review
2021-03-29 22:01:57 -07:00
Lofty
Patrick Urban
Marcelina Kościelnicka
Pepijn de Vos
Claire Xenia Wolf
Olivier Galibert
Eddie Hung
kittennbfive
ECP5-PCIe
Sylvain Munaut
Maciej Dudek
gatecat
Adam Greig
Michael Christensen
Stefan Riesenberger