34153adef4
Append (instead of over-writing) EXTRA_FLAGS
2019-02-15 11:56:51 -08:00
fc1c9aa11f
Update cells supported for verilog to FIRRTL conversion.
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Issue warning messages for missing parameterized modules and attempts to set initial values.
Replace simple "if (cell-type)" with "else if" chain.
Fix FIRRTL shift handling.
Add support for parameterized modules, $shift, $shiftx.
Handle default output file.
Deal with no top module.
Automatically run pmuxtree pass.
Allow EXTRA_FLAGS and SEED parameters to be set in the environment for tests/tools/autotest.mk.
Support FIRRTL regression testing in tests/tools/autotest.sh
Add xfirrtl files to test directories to exclude files from FIRRTL regression tests that are known to fail.
2019-02-15 11:14:17 -08:00
9666cca9dd
Remove asicworld tests for (unsupported) switch-level modelling
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-01-27 09:17:02 +01:00
0fc6e2bfcf
Merge pull request #770 from whitequark/opt_expr_cmp
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opt_expr: refactor and improve simplification of comparisons
2019-01-02 17:34:04 +01:00
bf8db55ef3
opt_expr: improve simplification of comparisons with large constants.
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The idea behind this simplification is that a N-bit signal X being
compared with an M-bit constant where M>N and the constant has Nth
or higher bit set, it either always succeeds or always fails.
However, the existing implementation only worked with one-hot signals
for some reason. It also printed incorrect messages.
This commit adjusts the simplification to have as much power as
possible, and fixes other bugs.
2019-01-02 15:45:28 +00:00
a91892bba4
cmp2lut: new techmap pass.
2019-01-02 07:53:31 +00:00
4fd458290c
opt_expr: refactor simplification of unsigned X<onehot and X>=onehot. NFCI.
2019-01-02 05:11:29 +00:00
9e9846a6ea
opt_expr: refactor simplification of signed X>=0 and X<0. NFCI.
2019-01-02 03:01:25 +00:00
8e53d2e0bf
opt_expr: simplify any unsigned comparisons with all-0 and all-1.
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Before this commit, only unsigned comparisons with all-0 would be
simplified. This commit also makes the code handling such comparisons
to be more rigorous and not abort on unexpected input.
2019-01-02 02:45:49 +00:00
42c356c49c
opt_lut: eliminate LUTs evaluating to constants or inputs.
2018-12-31 23:55:40 +00:00
99706b3bf4
Squelch a little more trailing whitespace
2018-12-29 12:46:54 +01:00
2a681909df
Merge pull request #724 from whitequark/equiv_opt
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equiv_opt: new command, for verifying optimization passes
2018-12-16 15:54:26 +01:00
7ff5a9db2d
equiv_opt: pass -D EQUIV when techmapping.
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This allows avoiding techmap crashes e.g. because of large memories
in white-box cell models.
2018-12-07 17:20:34 +00:00
c38ea9ae65
equiv_opt: new command, for verifying optimization passes.
2018-12-07 17:20:34 +00:00
7ec740b7ad
opt_lut: leave intact LUTs with cascade feeding module outputs.
2018-12-07 17:13:52 +00:00
7d1088afc4
Add missing .gitignore
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-12-06 07:29:37 +01:00
9ef078848a
gate2lut: new techlib, for converting Yosys gates to FPGA LUTs.
2018-12-05 17:13:27 +00:00
45cb6200af
opt_lut: add -dlogic, to avoid disturbing logic such as carry chains.
2018-12-05 16:30:37 +00:00
9e072ec21f
opt_lut: new pass, to combine LUTs for tighter packing.
2018-12-05 16:30:37 +00:00
6cd5b8b76b
Merge pull request #679 from udif/pr_syntax_error
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More meaningful SystemVerilog/Verilog parser error messages
2018-10-25 13:18:59 +02:00
536ae16c3a
Rename the generic "Syntax error" message from the Verilog/SystemVerilog parser into unique,
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meaningful info on the error.
Also add 13 compilation examples that triggers each of these messages.
2018-10-25 02:37:56 +03:00
397dfccb30
Support for SystemVerilog interfaces as a port in the top level module + test case
2018-10-20 11:58:25 +02:00
d5aac2650f
Basic test for checking correct synthesis of SystemVerilog interfaces
2018-10-18 22:40:53 +02:00
458a94059e
Support for 'modports' for System Verilog interfaces
2018-10-12 21:11:48 +02:00
75009ada3c
Synthesis support for SystemVerilog interfaces
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This time doing the changes mostly in AST before RTLIL generation
2018-10-12 21:11:36 +02:00
3d27c1cc80
Merge pull request #513 from udif/pr_reg_wire_error
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Add error checking for reg/wire/logic misuse - PR now passes 'make test' (plus a new test)
2018-08-15 13:35:41 +02:00
106af19b69
Fixed typo (sikp -> skip)
2018-06-05 22:41:27 +03:00
73d426bc87
Modified errors into warnings
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No longer false warnings for memories and assertions
2018-06-05 18:03:22 +03:00
80d9d15f1c
reg_wire_error test needs the -sv flag so it is run via a script so it had to be moved out of the tests/simple dir that only runs Verilog files
2018-06-05 18:00:06 +03:00
0295213bec
autotest.sh: Change from /bin/bash to /usr/bin/env bash
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This enables running tests on Unix systems which are not shipped with
bash installed in /bin/bash (eg *BSDs and Solaris).
2018-05-06 15:26:23 +02:00
5e49ee5c2d
Fix tests/simple/specify.v
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-03-27 14:34:00 +02:00
6378e2cd46
First draft of Verilog parser support for specify blocks and parameters.
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The only functionality of this code at the moment is to accept correct specify syntax and ignore it.
No part of the specify block is added to the AST
2018-03-27 14:34:00 +02:00
2b9c75f8e3
This PR should be the base for discussion, do not merge it yet!
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It correctly detects reg/wire mix and incorrect use on blocking,nonblocking assignments within blocks and assign statements.
What it DOES'T do:
Detect registers connected to output ports of instances.
Where it FAILS:
memorty nonblocking assignments causes spurious (I assume??) errors on yosys-generated "_ADDR", "_DATA", "EN" signals.
You can test it with tests/simple/reg_wire_error.v (look inside for the comments to enable/disable specific lines)
2018-03-11 23:09:34 +02:00
25e33d7ab8
Major redesign of Verific SVA importer
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-02-27 20:33:15 +01:00
6d12c83d36
Add support for SVA throughout via Verific
2018-02-21 13:09:47 +01:00
5c6247dfa6
Add support for SVA sequence concatenation ranges via verific
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-02-18 16:35:06 +01:00
9d963cd29c
Add support for SVA until statements via Verific
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-02-18 14:57:52 +01:00
bc8ab3ab44
Fix verific PRIM_SVA_AT handling in properties with PRIM_SVA_DISABLE_IFF
2018-02-15 15:26:37 +01:00
baddb017fe
Remove PSL example from tests/sva/
2017-10-20 13:16:24 +02:00
dbfd8460a9
Allow $size and $bits in verilog mode, actually check test case
2017-09-29 11:56:43 +02:00
e951ac0dfb
$size() now works correctly for all cases!
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It seems the issues was that AST_MULTIRANGE is converted into a multirange_dimensions[] array on the AST_MEMORY node directly.
2017-09-26 20:34:24 +03:00
6ddc6a7af4
$size() seems to work now with or without the optional parameter.
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Multidimensional arrays still don't work. I suspect the problem is that the array is flattened into a 1D array before $size() is evaluated.
2017-09-26 19:18:25 +03:00
2dea42e903
Added $bits() for memories as well.
2017-09-26 09:11:25 +03:00
17f8b41605
$size() now works with memories as well!
2017-09-26 08:36:45 +03:00
64eb8f29ad
Add $size() function. At the moment it works only on expressions, not on memories.
2017-09-26 06:25:42 +03:00
4cf890dac1
Add simple VHDL+PSL example
2017-07-28 17:39:43 +02:00
c1cfca8f54
Improve Verific SVA importer
2017-07-27 14:05:09 +02:00
877ff1f75e
Add counter.sv SVA test
2017-07-27 12:37:16 +02:00
b24f737759
Improve SVA tests, add Makefile and scripts
2017-07-27 11:42:05 +02:00
84f15260b5
Add more SVA test cases for future Verific work
2017-07-22 16:35:46 +02:00
Jim Lawson
Clifford Wolf
whitequark
Larry Doolittle
Udi Finkelstein
Ruben Undheim
Johnny Sorocil