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11957 Commits

Author SHA1 Message Date
Jannis Harder 1e67c3a3c2 opt_expr: Fix shift/shiftx optimizations 2022-11-30 18:24:25 +01:00
Jannis Harder fd56d1f79e opt_expr: Constant fold mux, pmux, bmux, demux, eqx, nex cells 2022-11-29 19:06:45 +01:00
Jannis Harder c08242ba41 opt_expr: Optimize bitwise logic ops with one fully const input 2022-11-29 19:06:45 +01:00
Jannis Harder 661fa5ff92 simplemap: Map `$xnor` to `$_XNOR_` cells 
The previous mapping to `$_XOR_` and `$_NOT_` predates the addition of
the `$_XNOR_` cell.
 2022-11-29 19:06:45 +01:00
github-actions[bot] f9db7c0599 Bump version 2022-11-29 00:18:02 +00:00
Jannis Harder 10e22608c0
Merge pull request #3565 from jix/sat-def-formal 
sat: Add -set-def-formal option to force defined $any* outputs
 2022-11-28 16:04:38 +01:00
Jannis Harder ed0e14820e sat: Add -set-def-formal option to force defined $any* outputs 2022-11-28 14:50:52 +01:00
github-actions[bot] 23e26ff661 Bump version 2022-11-26 00:16:21 +00:00
Miodrag Milanović fd01d9eb8b
Merge pull request #3561 from YosysHQ/tcl_shell 
Add TCL interactive shell mode
 2022-11-25 18:12:43 +01:00
Miodrag Milanović 448a796e15
Merge pull request #3560 from YosysHQ/verific_conf 
Support importing verilog configurations using Verific
 2022-11-25 17:40:57 +01:00
Miodrag Milanovic 2450e6be22 Add TCL interactive shell mode 2022-11-25 16:18:02 +01:00
Miodrag Milanovic f764cd1655 update documentation 2022-11-25 14:27:30 +01:00
Miodrag Milanovic b0be19c126 Support importing verilog configurations using Verific 2022-11-25 13:02:11 +01:00
github-actions[bot] c55c514cdb Bump version 2022-11-25 00:16:25 +00:00
KrystalDelusion b9b5899cce
Remove docs dependency on yosys repo (#3558) 
* Copies guidelines files into docs/ for website

* Copying manual/CHAPTER_Prog for new docs

* Copying manual/APPNOTE_011... for new docs

Also adding faketime to list of packages for website build.

Co-authored-by: KrystalDelusion <krystinedawn@yosyshq.com>
 2022-11-24 15:56:44 +01:00
Jannis Harder fc2f622a27
Merge pull request #3552 from daglem/fix-sv-c-array-dimensions 
Correct interpretation of SystemVerilog C-style array dimensions
 2022-11-23 15:12:17 +01:00
github-actions[bot] 13e4f343b9 Bump version 2022-11-22 00:18:29 +00:00
Jannis Harder 239ecf9185 Merge branch 'zachjs-master' 2022-11-21 17:47:43 +01:00
N. Engelhardt b64141f48b mention prerequisites in fsm_detect and fsm help 2022-11-21 16:07:23 +01:00
github-actions[bot] e56c689962 Bump version 2022-11-18 00:20:31 +00:00
gatecat b6467f0801 fabulous: Allow adding extra custom prims and map rules 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-11-17 13:34:58 +01:00
gatecat f111bbdf40 fabulous: improvements to the pass 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-11-17 13:34:58 +01:00
gatecat e3f9ff2679 fabulous: Unify and update primitives 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-11-17 13:34:58 +01:00
TaoBi22 12c22045b7 Introduce RegFile mappings 2022-11-17 13:34:58 +01:00
TaoBi22 2b07e01ea4 Replace synth call with components, reintroduce flags and correct vpr flag implementation 2022-11-17 13:34:58 +01:00
TaoBi22 df56178567 Reorder operations to load in primitive library before hierarchy pass 2022-11-17 13:34:58 +01:00
TaoBi22 da32f21b59 Add plib flag to specify custom primitive library path 2022-11-17 13:34:58 +01:00
TaoBi22 950dde3081 Remove flattening from FABulous pass 2022-11-17 13:34:58 +01:00
TaoBi22 8fdf4948a8 Remove ALL currently unused flags (some to be reintroduced later and passed through to synth) 2022-11-17 13:34:58 +01:00
TaoBi22 2e9480be24 Add synth_fabulous ScriptPass 2022-11-17 13:34:58 +01:00
github-actions[bot] 0516fd751c Bump version 2022-11-17 00:19:18 +00:00
Miodrag Milanovic 48659ee2bb Slowing down clock to have same metadata 2022-11-16 10:11:05 +01:00
github-actions[bot] 388611aac4 Bump version 2022-11-16 00:19:25 +00:00
Miodrag Milanovic 7de226878d faketime to make PDFs unique 2022-11-15 14:13:41 +01:00
KrystalDelusion a14dec79eb
Rst docs conversion (#3496) 
Rst docs conversion
 2022-11-15 12:55:22 +01:00
Miodrag Milanović 853f4bb3c6
Merge pull request #3547 from YosysHQ/update_abc 
Update ABC
 2022-11-14 16:53:29 +01:00
Dag Lem a862642fac Correct interpretation of SystemVerilog C-style array dimensions 
IEEE Std 1800™-2017 7.4.2 specifies that [size] is the same as [0:size-1].
 2022-11-13 07:41:25 +01:00
github-actions[bot] 553eb6ac1e Bump version 2022-11-10 00:19:39 +00:00
Emil J c75f12a989
Add missing memory width assert preventing division by zero (#3546) 2022-11-09 10:34:25 +01:00
Miodrag Milanovic 6403bfbd9f Update ABC 2022-11-09 08:48:31 +01:00
github-actions[bot] faa1c2e7fe Bump version 2022-11-09 00:20:01 +00:00
Miodrag Milanovic cb7299c3dc Next dev cycle 2022-11-08 07:57:48 +01:00
Miodrag Milanovic 7ce5011c24 Release version 0.23 2022-11-08 07:55:31 +01:00
Miodrag Milanovic 6758b7babc Update manual 2022-11-08 07:54:14 +01:00
github-actions[bot] 2cdbb85da6 Bump version 2022-11-08 00:20:00 +00:00
Jannis Harder 4cb923a4f5
Merge pull request #3544 from jix/cosim-ffinit 
sim: Run a comb-only update step to set past values during FST cosim
 2022-11-07 16:04:31 +01:00
Jannis Harder 9b4fba3870 sim: Run a comb-only update step to set past values during FST cosim 
The previous approach only initialized past_d and past_ad while for FST
cosim we also need to initialize the other past values like past_clk,
etc. Also to properly initialize them, we need to run a combinational
update step in case any of the wires feeding into the FF are private or
otherwise not part of the FST.
 2022-11-07 14:09:33 +01:00
Miodrag Milanovic cff42f0af5 Update CHANGELOG 2022-11-07 13:16:38 +01:00
Miodrag Milanović 96df99dafa
Merge pull request #3536 from YosysHQ/claire/vcdend 
Add extra time at the end of a sat VCD trace
 2022-11-07 13:15:57 +01:00
Miodrag Milanović bc0e69f5c8
Merge pull request #3543 from jix/fstdata-fixes 
fstdata: Fixes and improvements
 2022-11-07 13:15:42 +01:00