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Introduce RegFile mappings

This commit is contained in:
TaoBi22 2022-09-29 18:16:44 +01:00 committed by myrtle
parent 2b07e01ea4
commit 12c22045b7
4 changed files with 95 additions and 2 deletions
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2
techlibs/fabulous/Makefile.inc
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@ -7,4 +7,6 @@ $(eval $(call add_share_file,share/fabulous,techlibs/fabulous/prims.v))
$(eval $(call add_share_file,share/fabulous,techlibs/fabulous/prims_ff.v))
$(eval $(call add_share_file,share/fabulous,techlibs/fabulous/latches_map.v))
$(eval $(call add_share_file,share/fabulous,techlibs/fabulous/ff_map.v))
$(eval $(call add_share_file,share/fabulous,techlibs/fabulous/ram_regfile.txt))
$(eval $(call add_share_file,share/fabulous,techlibs/fabulous/regfile_map.v))

46
techlibs/fabulous/ram_regfile.txt Normal file
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@ -0,0 +1,46 @@
# Yosys doesn't support configurable sync/async ports.
# So we define three RAMs for 2xasync, 1xsync 1xasync and 2xsync
ram distributed $__REGFILE_AA_ {
abits 5;
width 4;
cost 6;
port sw "W" {
clock posedge "CLK";
}
port ar "A" {
}
port ar "B" {
}
}
ram distributed $__REGFILE_SA_ {
abits 5;
width 4;
cost 5;
port sw "W" {
clock posedge "CLK";
wrtrans all old;
}
port sr "A" {
clock posedge "CLK";
}
port ar "B" {
}
}
ram distributed $__REGFILE_SS_ {
abits 5;
width 4;
cost 4;
port sw "W" {
clock posedge "CLK";
wrtrans all old;
}
port sr "A" {
clock posedge "CLK";
}
port sr "B" {
clock posedge "CLK";
}
}

41
techlibs/fabulous/regfile_map.v Normal file
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@ -0,0 +1,41 @@
(* techmap_celltype = "$__REGFILE_[AS][AS]_" *)
module \$__REGFILE_XX_ (...);
parameter _TECHMAP_CELLTYPE_ = "";
localparam [0:0] B_SYNC = _TECHMAP_CELLTYPE_[15:8] == "S";
localparam [0:0] A_SYNC = _TECHMAP_CELLTYPE_[23:16] == "S";
localparam WIDTH = 4;
localparam ABITS = 5;
input [WIDTH-1:0] PORT_W_WR_DATA;
input [ABITS-1:0] PORT_W_ADDR;
input PORT_W_WR_EN;
output [WIDTH-1:0] PORT_A_RD_DATA;
input [ABITS-1:0] PORT_A_ADDR;
output [WIDTH-1:0] PORT_B_RD_DATA;
input [ABITS-1:0] PORT_B_ADDR;
// Unused - we have a shared clock - but keep techmap happy
input PORT_W_CLK;
input PORT_A_CLK;
input PORT_B_CLK;
input CLK_CLK;
RegFile_32x4 #(
.ConfigBits({B_SYNC, A_SYNC})
) _TECHMAP_REPLACE_ (
.D0(PORT_W_WR_DATA[0]), .D1(PORT_W_WR_DATA[1]), .D2(PORT_W_WR_DATA[2]), .D3(PORT_W_WR_DATA[3]),
.W_ADR0(PORT_W_ADDR[0]), .W_ADR1(PORT_W_ADDR[1]), .W_ADR2(PORT_W_ADDR[2]), .W_ADR3(PORT_W_ADDR[3]), .W_ADR4(PORT_W_ADDR[4]),
.W_en(PORT_W_WR_EN),
.AD0(PORT_A_RD_DATA[0]), .AD1(PORT_A_RD_DATA[1]), .AD2(PORT_A_RD_DATA[2]), .AD3(PORT_A_RD_DATA[3]),
.A_ADR0(PORT_A_ADDR[0]), .A_ADR1(PORT_A_ADDR[1]), .A_ADR2(PORT_A_ADDR[2]), .A_ADR3(PORT_A_ADDR[3]), .A_ADR4(PORT_A_ADDR[4]),
.BD0(PORT_B_RD_DATA[0]), .BD1(PORT_B_RD_DATA[1]), .BD2(PORT_B_RD_DATA[2]), .BD3(PORT_B_RD_DATA[3]),
.B_ADR0(PORT_B_ADDR[0]), .B_ADR1(PORT_B_ADDR[1]), .B_ADR2(PORT_B_ADDR[2]), .B_ADR3(PORT_B_ADDR[3]), .B_ADR4(PORT_B_ADDR[4]),
.CLK(CLK_CLK)
);
endmodule

8
techlibs/fabulous/synth_fabulous.cc
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@ -101,7 +101,6 @@ struct SynthPass : public ScriptPass
noshare = false;
}
// TODO: bring back relevant flags to carry through to synth call
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
string run_from, run_to;
@ -196,7 +195,6 @@ struct SynthPass : public ScriptPass
run("deminout");
// synth pass
run("proc");
run("opt_expr");
run("opt_clean");
run("check");
@ -219,8 +217,14 @@ struct SynthPass : public ScriptPass
run("memory -nomap" + memory_opts);
run("opt_clean");
// RegFile extraction
run("memory_libmap -lib +/fabulous/ram_regfile.txt");
run("techmap -map +/fabulous/regfile_map.v");
run("opt -fast -mux_undef -undriven -fine");
run("memory_map");
run("opt -undriven -fine");
run("opt -full");
run("techmap -map +/techmap.v");
run("opt -fast");