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Merge pull request #3552 from daglem/fix-sv-c-array-dimensions 

Correct interpretation of SystemVerilog C-style array dimensions
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Jannis Harder 2022-11-23 15:12:17 +01:00 committed by GitHub
parent 13e4f343b9 a862642fac
commit fc2f622a27
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1 changed files with 3 additions and 3 deletions
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6
frontends/verilog/verilog_parser.y
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@ -229,9 +229,9 @@ static AstNode *checkRange(AstNode *type_node, AstNode *range_node)
static void rewriteRange(AstNode *rangeNode)
{
if (rangeNode->type == AST_RANGE && rangeNode->children.size() == 1) {
// SV array size [n], rewrite as [n-1:0]
rangeNode->children[0] = new AstNode(AST_SUB, rangeNode->children[0], AstNode::mkconst_int(1, true));
rangeNode->children.push_back(AstNode::mkconst_int(0, false));
// SV array size [n], rewrite as [0:n-1]
rangeNode->children.push_back(new AstNode(AST_SUB, rangeNode->children[0], AstNode::mkconst_int(1, true)));
rangeNode->children[0] = AstNode::mkconst_int(0, false);
}
}