riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Correct interpretation of SystemVerilog C-style array dimensions 

IEEE Std 1800™-2017 7.4.2 specifies that [size] is the same as [0:size-1].
This commit is contained in:
Dag Lem 2022-11-13 07:41:25 +01:00
parent 553eb6ac1e
commit a862642fac
1 changed files with 3 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
frontends/verilog/verilog_parser.y
View File

@ -229,9 +229,9 @@ static AstNode *checkRange(AstNode *type_node, AstNode *range_node)
static void rewriteRange(AstNode *rangeNode)
{
if (rangeNode->type == AST_RANGE && rangeNode->children.size() == 1) {
// SV array size [n], rewrite as [n-1:0]
rangeNode->children[0] = new AstNode(AST_SUB, rangeNode->children[0], AstNode::mkconst_int(1, true));
rangeNode->children.push_back(AstNode::mkconst_int(0, false));
// SV array size [n], rewrite as [0:n-1]
rangeNode->children.push_back(new AstNode(AST_SUB, rangeNode->children[0], AstNode::mkconst_int(1, true)));
rangeNode->children[0] = AstNode::mkconst_int(0, false);
}
}