Clifford Wolf
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4f68a77e3f
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Improved read_verilog support for empty behavioral statements
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2015-02-10 12:17:29 +01:00 |
Clifford Wolf
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510deb3577
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Added "scc -expect <N> -nofeedback"
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2015-02-10 08:48:55 +01:00 |
Clifford Wolf
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adf4ecbc1f
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Some hashlib improvements
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2015-02-09 20:11:51 +01:00 |
Clifford Wolf
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68979d1395
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Various changes to release checklist
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2015-02-09 16:36:37 +01:00 |
Clifford Wolf
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a779a09771
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Fixed creation of command reference in manual
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2015-02-09 13:24:29 +01:00 |
Clifford Wolf
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e0ff4d1152
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We are now in 0.5+ development
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2015-02-09 13:13:51 +01:00 |
Clifford Wolf
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c3c9fbfb8c
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Yosys 0.5
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2015-02-09 12:49:52 +01:00 |
Clifford Wolf
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8901f405ca
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Bugfix in "make vcxsrc"
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2015-02-09 12:48:15 +01:00 |
Clifford Wolf
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b944fef925
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Updated command reference in manual
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2015-02-09 12:05:02 +01:00 |
Clifford Wolf
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85887de547
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Various presentation fixes
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2015-02-09 12:02:21 +01:00 |
Clifford Wolf
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f889e3d385
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Fixed iterator invalidation bug in "rename" command
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2015-02-09 00:18:36 +01:00 |
Clifford Wolf
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139648554d
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CodingReadme update
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2015-02-08 23:30:15 +01:00 |
Clifford Wolf
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07afb14318
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Fixed bug in "show -format .."
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2015-02-08 23:29:54 +01:00 |
Clifford Wolf
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183d4f8e71
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Added new APIs to changelog
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2015-02-08 21:14:52 +01:00 |
Clifford Wolf
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bcd8a2fc56
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Fixed eval_select_op() api
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2015-02-08 19:06:16 +01:00 |
Clifford Wolf
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09ee65a050
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Added eval_select_args() and eval_select_op()
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2015-02-08 18:56:06 +01:00 |
Clifford Wolf
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0fcc8c1467
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Minor "make vgtest" changes
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2015-02-08 15:13:51 +01:00 |
Clifford Wolf
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6d2f31c04a
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Various ModIndex improvements
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2015-02-08 14:23:12 +01:00 |
Clifford Wolf
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b10f0088d1
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Added Yosys 0.5 Changelog
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2015-02-08 12:03:51 +01:00 |
Clifford Wolf
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c3ce824af0
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Various updates to CodingReadme
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2015-02-08 12:03:51 +01:00 |
Clifford Wolf
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5170b86108
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Added equiv_add
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2015-02-08 11:59:38 +01:00 |
Clifford Wolf
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234a45a3d5
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Ignore explicit assignments to constants in HDL code
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2015-02-08 00:58:03 +01:00 |
Clifford Wolf
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c8305e3a6d
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Fixed a bug with autowire bit size
(removed leftover from when we tried to auto-size the wires)
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2015-02-08 00:48:23 +01:00 |
Clifford Wolf
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fbb16712f1
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fixed typo
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2015-02-08 00:16:59 +01:00 |
Clifford Wolf
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bbfc1bd7cf
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Added "yosys-config --build modname.so cppsources.."
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2015-02-08 00:14:07 +01:00 |
Clifford Wolf
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05d4223fb6
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Added SigSpec::has_const()
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2015-02-08 00:01:51 +01:00 |
Clifford Wolf
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0da320f151
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Cleanup in add_share_file make macro
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2015-02-08 00:01:31 +01:00 |
Clifford Wolf
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2ef812d67e
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Removed "make mklibyosys"
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2015-02-07 19:05:06 +01:00 |
Clifford Wolf
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743da01e9e
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Improved building of plugins
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2015-02-07 19:04:06 +01:00 |
Clifford Wolf
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cc400b279a
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Added "make uninstall"
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2015-02-07 17:46:46 +01:00 |
Clifford Wolf
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dce1fae777
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Added cell->known(), cell->input(portname), cell->output(portname)
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2015-02-07 11:40:19 +01:00 |
Clifford Wolf
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d5e30978e9
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Added "select -read"
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2015-02-06 10:01:22 +01:00 |
Clifford Wolf
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ac7d5e0658
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Auto-detect TCL version
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2015-02-05 23:39:26 +01:00 |
Clifford Wolf
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a038787c9b
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Added onehot attribute
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2015-02-04 18:52:54 +01:00 |
Clifford Wolf
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8805c24640
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Fixed opt_clean performance bug
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2015-02-04 16:34:06 +01:00 |
Clifford Wolf
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853e949c0e
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Disabled (unused) Xilinx tristate buffers
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2015-02-04 16:33:59 +01:00 |
Clifford Wolf
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a8f4a099b5
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Using design->selected_modules() in opt_*
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2015-02-03 23:45:01 +01:00 |
Clifford Wolf
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5b41470e15
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Skip blackbox modules in design->selected_modules()
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2015-02-03 23:12:23 +01:00 |
Clifford Wolf
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8514fe79db
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Added "yosys -L logfile"
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2015-02-03 23:12:23 +01:00 |
Clifford Wolf
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30ec64656b
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Merge branch 'master' of github.com:cliffordwolf/yosys
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2015-02-01 23:07:00 +01:00 |
Clifford Wolf
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bebbf2e5a4
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no support for 6-series xilinx devices
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2015-02-01 23:06:44 +01:00 |
Clifford Wolf
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6eb34038f4
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Merge pull request #48 from rubund/master
Fixed typos found by lintian
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2015-02-01 22:55:52 +01:00 |
Clifford Wolf
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893fe87a33
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Improved performance in equiv_simple
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2015-02-01 22:50:48 +01:00 |
Ruben Undheim
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49649d6ef0
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Fixed typos found by lintian
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2015-02-01 21:49:55 +01:00 |
Clifford Wolf
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3cbfa3815e
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Removed old XST-based xilinx examples
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2015-02-01 17:10:46 +01:00 |
Clifford Wolf
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816fe6bbe0
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Added Xilinx example for Basys3 board
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2015-02-01 17:09:34 +01:00 |
Clifford Wolf
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6978f3a77b
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Added EDIF backend support for multi-bit cell ports
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2015-02-01 15:43:35 +01:00 |
Clifford Wolf
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1b159bc955
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Added missing ports and parameters to xilinx brams
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2015-02-01 15:42:59 +01:00 |
Clifford Wolf
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1df81f92ce
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Added "make mklibyosys", some minor API changes
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2015-02-01 13:38:46 +01:00 |
Clifford Wolf
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3fe2441185
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Minor README changes
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2015-02-01 00:57:12 +01:00 |