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9887 Commits

Author SHA1 Message Date
Rupert Swarbrick 17b5f23f20 Use default copy constructor for RTLIL::SigBit 
There was a handwritten copy constructor, which I'm not sure was
actually legal C++ (it unconditionally read from the 'data' member of
a union, which wouldn't have been written if wire was true). It was
also a bit less efficient than the constructor you get from the
compiler by default (which is allowed to just copy the memory).

This gives a marginal (~0.25%) decrease in code size when compiled
with GCC 9.3.
 2020-05-26 13:18:01 +01:00
Rupert Swarbrick 8f87ccec9b Use c_str(), not str() for IdString/std::string == and != operators 
These operators work by fetching the string from the global string
table and then comparing with the std::string that was passed in as
rhs.

Using str() means that we create a std::string (strlen; malloc;
memcpy), compare for equality (another memcmp if they have the same
length) and then finally free the string.

Using c_str() means that we pass the const char* straight to
std::string's equality operator. This ends up as a call to
std::string::compare (the const char* flavour), which is essentially
strcmp.
 2020-05-26 12:27:15 +01:00
Eddie Hung 00c5ceb1f2 abc9_ops: -prep_xaiger exclude (* abc9_keep *) wires from toposort 2020-05-25 16:40:53 -07:00
Eddie Hung 1826370b3a xaiger: promote abc9_keep wires 2020-05-25 16:40:30 -07:00
Eddie Hung 1dce798dc5 tests: add ecp5 latch testcase with -abc9 2020-05-25 16:39:16 -07:00
Eddie Hung a7f2ef6d34
Merge pull request #2078 from YosysHQ/eddie/xilinx_sim_tidy 
xilinx: tidy up cells_sim.v a little
 2020-05-25 14:21:10 -07:00
Alberto Gonzalez 9847a4eea8
smtbmc and qbfsat: Add timeout option to set solver timeouts for Z3, Yices, and CVC4. 2020-05-25 20:39:30 +00:00
Alberto Gonzalez f9eef5e3f7
qbfsat: Add support for CVC4. 2020-05-25 20:39:03 +00:00
Alberto Gonzalez 54570a3978
qbfsat: Move SMT2 info statements back to the top of the file. 2020-05-25 20:38:29 +00:00
Alberto Gonzalez 903456c267
qbfsat: Add `-solver` option and allow choice of Z3 or Yices, making Yices the default. 
Ensures that "BV" is the logic whenever solving an exists-forall problem with Yices, moves the "(set-logic ...)" directive above any non-info line, sets the `ef-max-iters` parameter to a very high number when using Yices in exists-forall mode so as not to prematurely abandon difficult problems, and does not provide the incompatible "--incremental" Yices argument when in exists-forall mode.
 2020-05-25 20:38:29 +00:00
Eddie Hung 721283ac2a blackbox: re-use existing Module::makeblackbox() method 2020-05-25 10:53:49 -07:00
Eddie Hung 08221edbc1 tests: xilinx macc test to have initval, shorten BMC depth for runtime 2020-05-25 10:09:05 -07:00
Eddie Hung 60aa804915 tests: fix some test warnings 2020-05-25 10:07:58 -07:00
Eddie Hung 5b81df57c8 xilinx: tidy up cells_sim.v a little 2020-05-25 09:48:11 -07:00
Eddie Hung 59b355fb85
Merge pull request #2044 from YosysHQ/eddie/fix2037 
verilog: allow attributes on behavioural statements (including null statement)
 2020-05-25 09:14:00 -07:00
Eddie Hung 9c6d216a06 tests: add test for abc9 -dff removing a redundant flop entirely 2020-05-25 08:43:33 -07:00
Eddie Hung 7bad23f19c abc9_ops: -reintegrate to preserve flop names 2020-05-25 08:43:33 -07:00
Eddie Hung 8dd93e389e tests: add testcase for abc9 -dff preserving flop names 2020-05-25 08:43:33 -07:00
Eddie Hung 1ebf7155a7 aiger: cleanup 2020-05-25 08:43:33 -07:00
Eddie Hung 9e6c288e5a xaiger: cleanup 2020-05-25 08:43:33 -07:00
Eddie Hung c5a9abba11 verilog: move attr from simple_behav_stmt to its children to attach 2020-05-25 07:36:53 -07:00
Eddie Hung 95dcd7e785 test: add attribute-before-stmt test from @nakengelhardt 2020-05-25 07:36:53 -07:00
Eddie Hung 1c117ac023 verilog: do not warn for attributes on null statements 2020-05-25 07:36:53 -07:00
Eddie Hung 29d84339bf tests: add an generate-else test too 2020-05-25 07:36:53 -07:00
Eddie Hung 88bddb37c9 verilog: handle empty generate statement by removing gen_stmt_or_null... 
... rule which causes a s/r conflict. Now we get an empty genblock,
which should be okay.
 2020-05-25 07:36:53 -07:00
Eddie Hung d21a07c7b5 verilog: fix #2037 by permitting (and freeing) attributes on null stmt 2020-05-25 07:36:53 -07:00
Eddie Hung 589775538c tests: add #2037 testcase 2020-05-25 07:36:53 -07:00
clairexen ae11156c90
Merge pull request #2015 from boqwxp/qbfsat-bisection 
qbfsat: Add an iterative bisection optimization method and make it the default.
 2020-05-25 15:50:18 +02:00
Eddie Hung 89ed34fe55
Merge pull request #2075 from YosysHQ/eddie/xaiger_cleanup 
xaiger: do not derive cells
 2020-05-24 10:10:50 -07:00
Eddie Hung 33b03ce904 xaiger: add testcase 2020-05-24 08:48:23 -07:00
Eddie Hung d64df21630 xaiger: do not derive cells 2020-05-24 08:17:30 -07:00
Eddie Hung 227c3ff310
Merge pull request #2074 from YosysHQ/eddie/ecp5_cleanup 
ecp5: cleanup unused +/ecp5/abc9_model.v
 2020-05-23 09:28:42 -07:00
Eddie Hung 76e0cc8276 ecp5: cleanup unused +/ecp5/abc9_model.v 2020-05-23 08:17:40 -07:00
Alberto Gonzalez ac41f8a9c7
qbfsat: Remove cruft inadvertently left untouched in commit 86fc49a9d6. 2020-05-23 00:53:09 +00:00
Alberto Gonzalez aea0fd5ed4
qbfsat: Add bisection mode and make it the default. 
Also adds `-nooptimize` and reorganizes `qbfsat.cc` a bit.
 2020-05-23 00:53:09 +00:00
whitequark 721040df76
Merge pull request #2072 from whitequark/cxxrtl-dont-purge 
cxxrtl: get rid of -O5 aka `opt_clean -purge` optimization level
 2020-05-22 20:08:39 +00:00
whitequark 281c96856a cxxrtl: get rid of -O5 aka `opt_clean -purge` optimization level. 
This isn't actually necessary anymore after scheduling was improved,
and `clean -purge` disrupts the mapping between wires in the input
RTLIL netlist and the output CXXRTL code.
 2020-05-22 19:08:30 +00:00
Eddie Hung 4f0f321169 abc9_ops: update comment 2020-05-21 21:39:13 -07:00
Eddie Hung 574812d9a5
Merge pull request #2057 from YosysHQ/eddie/fix_task_attr 
verilog: support attributes before (not after) task identifier (but 13 s/r conflicts)
 2020-05-21 11:00:36 -07:00
Eddie Hung 38e858af8d
Update frontends/verilog/verilog_parser.y 
Co-authored-by: Alberto Gonzalez <61295559+boqwxp@users.noreply.github.com>
 2020-05-21 09:10:56 -07:00
Miodrag Milanović 637650597b
Merge pull request #2059 from boqwxp/logger-vector-to-dict 
log: Use `dict` instead of `std::vector<std::pair>` for `log_expect_{error, warning, log}` to better express the intent that each element is unique.
 2020-05-21 15:36:30 +02:00
N. Engelhardt 026fed3135
Merge pull request #2046 from PeterCrozier/trap 
Extend YS_DEBUGTRAP to MacOS.
 2020-05-20 10:12:24 +02:00
N. Engelhardt 7c4e580f8f
Merge pull request #2054 from boqwxp/fix-smtbmc 
smtbmc: Fix return status handling.
 2020-05-20 08:55:36 +02:00
Alberto Gonzalez 6eea4b3d79
kernel: Try an order-independent approach to hashing `dict`. 
Co-Authored-By: David Shah <dave@ds0.me>
Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
 2020-05-19 23:32:53 +00:00
Alberto Gonzalez 1053032a81
smtbmc: Fix typo in error message. 
Co-Authored-By: N. Engelhardt <nak@symbioticeda.com>
 2020-05-19 16:13:44 +00:00
Martin ae887c49f9 Merge branch 'master' of https://github.com/hackfin/yosys 2020-05-19 11:14:51 +02:00
Martin 43c34a7828 idict handling in wrapper 
- Also, re-applied no-line-break workaround to rtlil.h to make parser
  catch all methods.
 2020-05-19 11:13:49 +02:00
Marcelina Kościelnicka aee439360b Add force_downto and force_upto wire attributes. 
Fixes #2058.
 2020-05-19 01:42:40 +02:00
Eddie Hung 2d573a0ff6
Merge pull request #1926 from YosysHQ/eddie/abc9_auto_dff 
abc9: support seq synthesis when module has (* abc9_flop *) and bypass non-combinatorial (* abc9_box *)
 2020-05-18 08:06:50 -07:00
Alberto Gonzalez 049e4caceb
firrtl: Accept techmapped cell types in FIRRTL backend. 2020-05-17 10:03:11 +00:00