1158bbf7db
Fix small typos in documentation for hierarchy command
2020-05-28 11:39:44 +01:00
2384a59e2a
Merge pull request #2051 from Xiretza/makefile-cd-warning
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Suppress warning during initial clone of ABC repo
2020-05-28 10:00:49 +00:00
736ccb2ad5
Merge pull request #2031 from epfl-vlsc/master
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Add extmodule support to firrtl backend
2020-05-28 09:59:17 +00:00
2974183855
Merge pull request #2063 from boqwxp/techmapped-firrtl
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firrtl: Accept techmapped cell types in FIRRTL backend.
2020-05-28 09:42:58 +00:00
02bb52eef1
Merge pull request #2088 from rswarbrick/count-at
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Minor optimisation in Module::wire() and Module::cell()
2020-05-28 09:41:17 +00:00
fdca785eda
Merge pull request #2087 from rswarbrick/lex-warn
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Silence spurious warning in Verilog lexer when compiling with GCC
2020-05-28 09:41:04 +00:00
8a44a46806
Merge pull request #2086 from rswarbrick/sigbit
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Use default copy constructor for RTLIL::SigBit
2020-05-28 09:40:49 +00:00
5b62dbb0af
Merge pull request #2084 from rswarbrick/c_str
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Use c_str(), not str() for IdString/std::string == and != operators
2020-05-28 09:40:35 +00:00
b651352193
Merge pull request #2090 from whitequark/cxxrtl-fixes
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Minor fixes for CXXRTL
2020-05-26 22:18:14 +00:00
0bf6b164be
cxxrtl: make logging a little bit nicer.
2020-05-26 21:37:32 +00:00
e9c07e2bda
cxxrtl: add missing parts of commit 281c9685.
2020-05-26 21:34:20 +00:00
6aa0f72ae9
Silence spurious warning in Verilog lexer when compiling with GCC
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The chosen value shouldn't have any effect. I considered something
clearly wrong like -1, but there's no checking inside the generated
lexer, and I suspect this will cause even weirder bugs if triggered
than just setting it to INITIAL.
2020-05-26 17:54:57 +01:00
7ff306ccdb
Minor optimisation in Module::wire() and Module::cell()
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The existing code does a search to figure out whether id is in the
dict (with the call to count()), and then looks it up again to get the
result (with the call to at()). This version calls find() instead,
avoiding the double lookup.
Code size increases slightly (6kb). I think this is because the
contents of find() are getting inlined, and then inlined into lots of
the callsites for cell() and wire().
Looking at the compiled code before this patch, you just get
a (non-inlined) call to count() followed by a call to at(). After the
patch, the contents of find() have been inlined (so you see do_hash,
then do_lookup). The result for each function is about 30 bytes / 40%
bigger, which presumably also enlarges call-sites that inline it.
2020-05-26 16:07:36 +01:00
17b5f23f20
Use default copy constructor for RTLIL::SigBit
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There was a handwritten copy constructor, which I'm not sure was
actually legal C++ (it unconditionally read from the 'data' member of
a union, which wouldn't have been written if wire was true). It was
also a bit less efficient than the constructor you get from the
compiler by default (which is allowed to just copy the memory).
This gives a marginal (~0.25%) decrease in code size when compiled
with GCC 9.3.
2020-05-26 13:18:01 +01:00
8f87ccec9b
Use c_str(), not str() for IdString/std::string == and != operators
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These operators work by fetching the string from the global string
table and then comparing with the std::string that was passed in as
rhs.
Using str() means that we create a std::string (strlen; malloc;
memcpy), compare for equality (another memcmp if they have the same
length) and then finally free the string.
Using c_str() means that we pass the const char* straight to
std::string's equality operator. This ends up as a call to
std::string::compare (the const char* flavour), which is essentially
strcmp.
2020-05-26 12:27:15 +01:00
a7f2ef6d34
Merge pull request #2078 from YosysHQ/eddie/xilinx_sim_tidy
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xilinx: tidy up cells_sim.v a little
2020-05-25 14:21:10 -07:00
08221edbc1
tests: xilinx macc test to have initval, shorten BMC depth for runtime
2020-05-25 10:09:05 -07:00
5b81df57c8
xilinx: tidy up cells_sim.v a little
2020-05-25 09:48:11 -07:00
59b355fb85
Merge pull request #2044 from YosysHQ/eddie/fix2037
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verilog: allow attributes on behavioural statements (including null statement)
2020-05-25 09:14:00 -07:00
c5a9abba11
verilog: move attr from simple_behav_stmt to its children to attach
2020-05-25 07:36:53 -07:00
95dcd7e785
test: add attribute-before-stmt test from @nakengelhardt
2020-05-25 07:36:53 -07:00
1c117ac023
verilog: do not warn for attributes on null statements
2020-05-25 07:36:53 -07:00
29d84339bf
tests: add an generate-else test too
2020-05-25 07:36:53 -07:00
88bddb37c9
verilog: handle empty generate statement by removing gen_stmt_or_null...
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... rule which causes a s/r conflict. Now we get an empty genblock,
which should be okay.
2020-05-25 07:36:53 -07:00
d21a07c7b5
verilog: fix #2037 by permitting (and freeing) attributes on null stmt
2020-05-25 07:36:53 -07:00
589775538c
tests: add #2037 testcase
2020-05-25 07:36:53 -07:00
ae11156c90
Merge pull request #2015 from boqwxp/qbfsat-bisection
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qbfsat: Add an iterative bisection optimization method and make it the default.
2020-05-25 15:50:18 +02:00
89ed34fe55
Merge pull request #2075 from YosysHQ/eddie/xaiger_cleanup
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xaiger: do not derive cells
2020-05-24 10:10:50 -07:00
33b03ce904
xaiger: add testcase
2020-05-24 08:48:23 -07:00
d64df21630
xaiger: do not derive cells
2020-05-24 08:17:30 -07:00
227c3ff310
Merge pull request #2074 from YosysHQ/eddie/ecp5_cleanup
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ecp5: cleanup unused +/ecp5/abc9_model.v
2020-05-23 09:28:42 -07:00
76e0cc8276
ecp5: cleanup unused +/ecp5/abc9_model.v
2020-05-23 08:17:40 -07:00
ac41f8a9c7
qbfsat: Remove cruft inadvertently left untouched in commit 86fc49a9d6.
2020-05-23 00:53:09 +00:00
aea0fd5ed4
qbfsat: Add bisection mode and make it the default.
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Also adds `-nooptimize` and reorganizes `qbfsat.cc` a bit.
2020-05-23 00:53:09 +00:00
721040df76
Merge pull request #2072 from whitequark/cxxrtl-dont-purge
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cxxrtl: get rid of -O5 aka `opt_clean -purge` optimization level
2020-05-22 20:08:39 +00:00
281c96856a
cxxrtl: get rid of -O5 aka `opt_clean -purge` optimization level.
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This isn't actually necessary anymore after scheduling was improved,
and `clean -purge` disrupts the mapping between wires in the input
RTLIL netlist and the output CXXRTL code.
2020-05-22 19:08:30 +00:00
4f0f321169
abc9_ops: update comment
2020-05-21 21:39:13 -07:00
574812d9a5
Merge pull request #2057 from YosysHQ/eddie/fix_task_attr
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verilog: support attributes before (not after) task identifier (but 13 s/r conflicts)
2020-05-21 11:00:36 -07:00
38e858af8d
Update frontends/verilog/verilog_parser.y
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Co-authored-by: Alberto Gonzalez <61295559+boqwxp@users.noreply.github.com>
2020-05-21 09:10:56 -07:00
637650597b
Merge pull request #2059 from boqwxp/logger-vector-to-dict
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log: Use `dict` instead of `std::vector<std::pair>` for `log_expect_{error, warning, log}` to better express the intent that each element is unique.
2020-05-21 15:36:30 +02:00
026fed3135
Merge pull request #2046 from PeterCrozier/trap
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Extend YS_DEBUGTRAP to MacOS.
2020-05-20 10:12:24 +02:00
7c4e580f8f
Merge pull request #2054 from boqwxp/fix-smtbmc
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smtbmc: Fix return status handling.
2020-05-20 08:55:36 +02:00
1053032a81
smtbmc: Fix typo in error message.
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Co-Authored-By: N. Engelhardt <nak@symbioticeda.com>
2020-05-19 16:13:44 +00:00
aee439360b
Add force_downto and force_upto wire attributes.
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Fixes #2058 .
2020-05-19 01:42:40 +02:00
2d573a0ff6
Merge pull request #1926 from YosysHQ/eddie/abc9_auto_dff
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abc9: support seq synthesis when module has (* abc9_flop *) and bypass non-combinatorial (* abc9_box *)
2020-05-18 08:06:50 -07:00
049e4caceb
firrtl: Accept techmapped cell types in FIRRTL backend.
2020-05-17 10:03:11 +00:00
fa8cb3e35d
Revert "Add support for non-power-of-two mem chunks in verific importer"
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This reverts commit 173aa27ca5
2020-05-17 11:31:11 +02:00
8297afe925
log: Use `dict` instead of `std::vector<std::pair>` for `log_expect_{error, warning, log}` to better express the intent that each element is unique.
2020-05-15 00:55:32 +00:00
67fc0c3698
abc9: use (* abc9_keep *) instead of (* abc9_scc *); apply to $_DFF_?_
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instead of moving them to $__ prefix
2020-05-14 16:44:35 -07:00
7101ef550b
verilog: attributes before task enable (but 13 s/r conflicts)
2020-05-14 16:10:11 -07:00
Rupert Swarbrick
whitequark
Eddie Hung
clairexen
Alberto Gonzalez
Miodrag Milanović
N. Engelhardt
Marcelina Kościelnicka