caravel/openlane
Kareem Farid c84e1393e7
updates to top level caravel (#59)
* REVERT ME: temporarily match simple_por pin in verilog with lef

* - update configs
- add patch file for power routing def

* - update the following caravel toplevel views
    - gl
    - mag
    - def
- add caravel power routing def

* Apply automatic changes to Manifest and README.rst

* update gl mag and def for caravel

* Revert "REVERT ME: temporarily match simple_por pin in verilog with lef"

This reverts commit b70c27c69f.

* update caravel gds

* Apply automatic changes to Manifest and README.rst

* Added text and logo cells back into the caravel top level.  Put an
isolated ground marker layer on the xres_buf layout.  Corrected
the power supply pin names on the gate level verilog netlist of
simple_por in caravel.v.  Updated the copyright block text.
Corrected DRC errors in the top level routing.

Co-authored-by: Tim Edwards <tim@opencircuitdesign.com>
2022-04-08 09:31:33 -07:00
..
caravan [DATA] Add caravan layout 2021-11-22 23:10:25 +02:00
caravel updates to top level caravel (#59) 2022-04-08 09:31:33 -07:00
caravel_clocking [DATA] Update caravel_clocking 2021-12-07 13:36:56 +02:00
chip_io [DATA] Add chip_io views with the fixed clamped3 pad 2021-11-17 16:42:36 +02:00
chip_io_alt [DATA] Add user_analog_project_wrapper and chip_io_alt gds/lef views 2021-11-22 23:08:25 +02:00
digital_pll [DATA] Update caravel_clocking/digital_pll/housekeeping 2021-12-02 21:09:43 +02:00
gpio_control_block - update gpio_control_block config (#57) 2022-04-08 09:27:51 -07:00
gpio_defaults_block Update gpio_defaults_block to align the pins with the gpio_control_block 2021-11-05 23:27:32 +02:00
gpio_logic_high harden gpio_control_block 2021-11-04 16:19:12 +02:00
housekeeping [DATA] Update caravel_clocking/digital_pll/housekeeping 2021-12-02 21:09:43 +02:00
mgmt_protect Mgmt protect update (#58) 2022-04-08 09:29:49 -07:00
mprj2_logic_high [DATA] Add views for the mgmt_protect 2021-11-15 13:21:52 +02:00
mprj_logic_high [DATA] Add views for the mgmt_protect 2021-11-15 13:21:52 +02:00
spare_logic_block [DATA] Add spare_logic_block 2021-11-24 20:36:23 +02:00
user_analog_project_wrapper Move Rectify To Caravel 2022-01-15 23:27:38 +02:00
user_id_programming [DATA] Add gds/lef/maglef/gl views for the user_id_programming block 2021-11-15 18:17:32 +02:00
user_project_wrapper [DATA] Add digital user project wrapper 2021-11-17 13:13:11 +02:00
.gitignore [DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz 2021-11-15 15:50:43 +02:00
Makefile Introduction of PDK variable (#39) 2022-04-08 09:05:58 -07:00
README.rst Apply automatic changes to Manifest and README.rst 2021-12-17 01:51:53 +00:00
README.src.rst add documentation 2021-12-16 17:51:16 -08:00
chip_dimensions.txt [DATA] Add initial caravel layout 2021-11-19 01:37:10 +02:00
openlane.md Update openlane.md 2022-01-14 11:27:37 -05:00

README.src.rst

.. raw:: html

   <!---
   # SPDX-FileCopyrightText: 2020 Efabless Corporation
   #
   # Licensed under the Apache License, Version 2.0 (the "License");
   # you may not use this file except in compliance with the License.
   # You may obtain a copy of the License at
   #
   #      http://www.apache.org/licenses/LICENSE-2.0
   #
   # Unless required by applicable law or agreed to in writing, software
   # distributed under the License is distributed on an "AS IS" BASIS,
   # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
   # See the License for the specific language governing permissions and
   # limitations under the License.
   #
   # SPDX-License-Identifier: Apache-2.0
   -->


.. include:: ../docs/source/caravel-with-openlane.rst