..
__uprj_analog_netlists.v
Seeding with documentation of pinout and verilog RTL (mostly unchanged
2021-10-12 16:31:42 -04:00
__uprj_netlists.v
Seeding with documentation of pinout and verilog RTL (mostly unchanged
2021-10-12 16:31:42 -04:00
__user_analog_project_wrapper.v
cocotb - updates related to enable simulating caraval using iverilog ( #320 )
2022-10-21 07:43:34 -07:00
__user_project_gpio_example.v
Add gpio_all_bidir_user test
2022-10-10 15:59:20 -07:00
__user_project_la_example.v
add test la test
2022-10-08 06:25:26 -07:00
__user_project_wrapper.v
fix bug of wrapper ack
2022-10-11 06:02:44 -07:00
buff_flash_clkrst.v
connected rest of buffers to power
2022-10-17 01:15:46 +02:00
caravan.v
Fixes to caravan for LVS and ERC ( #330 )
2022-10-21 14:28:53 -07:00
caravan_netlists.v
Added buffers to the top level, inside a macro called
2022-10-13 13:29:27 -04:00
caravan_openframe.v
Renamed the poorly and awkwardly named "sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped"
2021-10-31 21:43:09 -04:00
caravan_power_routing.v
Caravan redesign ( #321 )
2022-10-21 07:37:41 -07:00
caravel.v
Move decleration of some signal in caravel.v to fix error in iverilog
2022-10-20 06:26:55 -07:00
caravel_clocking.v
Changed the synchronized reset to occur on the clock falling edge
2021-12-02 14:26:59 -05:00
caravel_logo.v
reharden: caravel
2022-10-16 15:44:27 -07:00
caravel_motto.v
reharden: caravel
2022-10-16 15:44:27 -07:00
caravel_netlists.v
Added buffers to the top level, inside a macro called
2022-10-13 13:29:27 -04:00
caravel_openframe.v
Renamed the poorly and awkwardly named "sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped"
2021-10-31 21:43:09 -04:00
caravel_power_routing.v
reharden!: caravel
2022-10-10 04:51:05 -07:00
chip_io.v
some rtl changes
2022-10-10 05:13:48 -07:00
chip_io_alt.v
Caravan redesign ( #321 )
2022-10-21 07:37:41 -07:00
clock_div.v
Fixed one bad error in clock_div which had been done without my
2021-12-06 21:37:51 -05:00
constant_block.v
Modified the GPIO control block to buffer the constant high/low outputs.
2022-09-20 17:49:08 -04:00
copyright_block.v
reharden: caravel
2022-10-16 15:44:27 -07:00
debug_regs.v
Add gpio_all_o_user test
2022-10-09 07:53:25 -07:00
defines.v
Update storage testbench to work with one 2K block
2021-11-12 17:14:21 +02:00
digital_pll.v
reharden!: digital_pll
2022-10-17 10:56:01 -07:00
digital_pll_controller.v
Seeding with documentation of pinout and verilog RTL (mostly unchanged
2021-10-12 16:31:42 -04:00
gpio_control_block.v
add sky130_fd_sc_hd__macro_sparecell inside gpio_control_block rtl
2022-10-10 05:24:25 -07:00
gpio_defaults_block.v
Implemented a system for setting the GPIO power-on defaults through
2021-10-23 17:18:30 -04:00
gpio_logic_high.v
Seeding with documentation of pinout and verilog RTL (mostly unchanged
2021-10-12 16:31:42 -04:00
gpio_signal_buffering.v
Once again. . . Rewrote the RTL verilog so that only signals
2022-10-16 12:49:44 -04:00
gpio_signal_buffering_alt.v
Corrected the verilog and the layout for the caravan version of the
2022-10-16 21:06:27 -04:00
housekeeping.v
Syntax changes that are non-functional from a synthesis perspective. ( #324 )
2022-10-21 10:10:20 -07:00
housekeeping_spi.v
Syntax changes that are non-functional from a synthesis perspective. ( #324 )
2022-10-21 10:10:20 -07:00
mgmt_protect.v
fix some typos on mgmt_protect
2022-10-05 03:27:46 -07:00
mgmt_protect_hv.v
Seeding with documentation of pinout and verilog RTL (mostly unchanged
2021-10-12 16:31:42 -04:00
mprj2_logic_high.v
Seeding with documentation of pinout and verilog RTL (mostly unchanged
2021-10-12 16:31:42 -04:00
mprj_io.v
Fix typo at mprj_io ( #168 )
2022-10-10 12:11:05 -07:00
mprj_logic_high.v
Revised the management protect block to include protections against
2021-10-27 19:36:43 -04:00
open_source.v
reharden: caravel
2022-10-16 15:44:27 -07:00
pads.v
Modified the GPIO control block to buffer the constant high/low outputs.
2022-09-20 17:49:08 -04:00
ring_osc2x13.v
Seeding with documentation of pinout and verilog RTL (mostly unchanged
2021-10-12 16:31:42 -04:00
simple_por.v
Modified simple_por.v RTL to avoid the wire declaration that "cvc"
2021-12-08 12:16:19 -05:00
spare_logic_block.v
Revised the spare logic block to make sure that all inputs are
2021-11-24 09:34:52 -05:00
user_defines.v
Split the layout of the GPIO defaults block into three versions, for the
2021-11-06 13:28:26 -04:00
user_id_programming.v
Implemented a system for setting the GPIO power-on defaults through
2021-10-23 17:18:30 -04:00
user_id_textblock.v
reharden: caravel
2022-10-16 15:44:27 -07:00
xres_buf.v
Renamed the poorly and awkwardly named "sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped"
2021-10-31 21:43:09 -04:00
d9260dc533