mirror of https://github.com/efabless/caravel.git
154 lines
5.2 KiB
Verilog
154 lines
5.2 KiB
Verilog
// SPDX-FileCopyrightText: 2020 Efabless Corporation
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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// SPDX-License-Identifier: Apache-2.0
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`default_nettype none
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/*
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*-------------------------------------------------------------
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*
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* user_analog_project_wrapper
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*
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* This wrapper enumerates all of the pins available to the
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* user for the user analog project.
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*
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*-------------------------------------------------------------
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*/
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module user_analog_project_wrapper (
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`ifdef USE_POWER_PINS
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inout vdda1, // User area 1 3.3V supply
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inout vdda2, // User area 2 3.3V supply
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inout vssa1, // User area 1 analog ground
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inout vssa2, // User area 2 analog ground
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inout vccd1, // User area 1 1.8V supply
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inout vccd2, // User area 2 1.8v supply
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inout vssd1, // User area 1 digital ground
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inout vssd2, // User area 2 digital ground
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`endif
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// Wishbone Slave ports (WB MI A)
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input wb_clk_i,
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input wb_rst_i,
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input wbs_stb_i,
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input wbs_cyc_i,
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input wbs_we_i,
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input [3:0] wbs_sel_i,
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input [31:0] wbs_dat_i,
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input [31:0] wbs_adr_i,
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output wbs_ack_o,
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output [31:0] wbs_dat_o,
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// Logic Analyzer Signals
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input [127:0] la_data_in,
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output [127:0] la_data_out,
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input [127:0] la_oenb,
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/* GPIOs. There are 27 GPIOs, on either side of the analog.
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* These have the following mapping to the GPIO padframe pins
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* and memory-mapped registers, since the numbering remains the
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* same as caravel but skips over the analog I/O:
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*
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* io_in/out/oeb/in_3v3 [26:14] <---> mprj_io[37:25]
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* io_in/out/oeb/in_3v3 [13:0] <---> mprj_io[13:0]
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*
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* When the GPIOs are configured by the Management SoC for
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* user use, they have three basic bidirectional controls:
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* in, out, and oeb (output enable, sense inverted). For
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* analog projects, a 3.3V copy of the signal input is
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* available. out and oeb must be 1.8V signals.
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*/
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input [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_in,
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input [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_in_3v3,
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output [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_out,
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output [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_oeb,
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/* Analog (direct connection to GPIO pad---not for high voltage or
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* high frequency use). The management SoC must turn off both
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* input and output buffers on these GPIOs to allow analog access.
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* These signals may drive a voltage up to the value of VDDIO
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* (3.3V typical, 5.5V maximum).
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*
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* Note that analog I/O is not available on the 7 lowest-numbered
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* GPIO pads, and so the analog_io indexing is offset from the
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* GPIO indexing by 7, as follows:
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*
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* gpio_analog/noesd [17:7] <---> mprj_io[35:25]
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* gpio_analog/noesd [6:0] <---> mprj_io[13:7]
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*
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*/
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inout [`MPRJ_IO_PADS-`ANALOG_PADS-10:0] gpio_analog,
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inout [`MPRJ_IO_PADS-`ANALOG_PADS-10:0] gpio_noesd,
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/* Analog signals, direct through to pad. These have no ESD at all,
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* so ESD protection is the responsibility of the designer.
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*
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* user_analog[10:0] <---> mprj_io[24:14]
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*
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*/
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inout [`ANALOG_PADS-1:0] io_analog,
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/* Additional power supply ESD clamps, one per analog pad. The
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* high side should be connected to a 3.3-5.5V power supply.
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* The low side should be connected to ground.
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*
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* clamp_high[2:0] <---> mprj_io[20:18]
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* clamp_low[2:0] <---> mprj_io[20:18]
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*
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*/
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inout [2:0] io_clamp_high,
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inout [2:0] io_clamp_low,
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// Independent clock (on independent integer divider)
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input user_clock2,
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// User maskable interrupt signals
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output [2:0] user_irq
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);
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// Dummy assignment so that we can take it through the openlane flow
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assign io_out = io_in;
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// splitting the address space to user address space and debug address space
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// debug address space are the last 2 registers of user_project_wrapper address space
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wire wbs_cyc_i_user;
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wire wbs_ack_o_user;
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wire [31:0] wbs_dat_o_user;
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wire wbs_cyc_i_debug;
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wire wbs_ack_o_debug;
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wire [31:0] wbs_dat_o_debug;
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assign wbs_cyc_i_user = (wbs_adr_i[31:3] != 29'h601FFFF) ? wbs_cyc_i : 0;
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assign wbs_cyc_i_debug = (wbs_adr_i[31:3] == 29'h601FFFF) ? wbs_cyc_i : 0;
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assign wbs_ack_o = (wbs_adr_i[31:3] == 28'h601FFFF) ? wbs_ack_o_debug : wbs_ack_o_user;
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assign wbs_dat_o = (wbs_adr_i[31:3] == 28'h601FFFF) ? wbs_dat_o_debug : wbs_dat_o_user;
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assign wbs_ack_o_user = 0;
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debug_regs debug(
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.wb_clk_i(wb_clk_i),
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.wb_rst_i(wb_rst_i),
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.wbs_cyc_i(wbs_cyc_i_debug),
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.wbs_stb_i(wbs_stb_i),
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.wbs_we_i(wbs_we_i),
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.wbs_sel_i(wbs_sel_i),
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.wbs_adr_i(wbs_adr_i),
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.wbs_dat_i(wbs_dat_i),
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.wbs_ack_o(wbs_ack_o_debug),
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.wbs_dat_o(wbs_dat_o_debug)
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);
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endmodule // user_analog_project_wrapper
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