Commit Graph

239 Commits

Author SHA1 Message Date
mo-hosni b5010be8a7 Update Openlane views 2022-10-27 09:53:45 -07:00
mo-hosni 2d61e593aa Decreased distances from pins to and gates in mgmt_protect 2022-10-27 08:20:57 -07:00
marwaneltoukhy 66b7293817 signoff views for caravan 2022-10-22 07:01:29 -07:00
kareem c5c51bdd4a reharden: caravan
~ reimplement after chip_io_alt lef view update
2022-10-22 06:03:44 -07:00
kareem 0be31a26c1 reharden: caravan
~ reimplement after rtl changes
2022-10-22 02:52:02 -07:00
R. Timothy Edwards d9260dc533
Fixes to caravan for LVS and ERC (#330)
* Corrected missing part of porb_h route in the caravan chip_io_alt
layout.  Correcting the indexing of the "mprj_io_one" connections
to "mgmt_io_oeb" on the left-hand side of caravan, as they were
connecting back to the right side and making a mess of wiring,
instead of being wired locally directly to the nearest I/O.

* Apply automatic changes to Manifest and README.rst

* Corrected the unconnected mgmt_io_in inputs to housekeeping on
the caravan chip (which correspond to the GPIOs that do not exist
in caravan) by connecting them to the "zero" outputs of the
closest GPIO control blocks.

* Apply automatic changes to Manifest and README.rst

Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com>
2022-10-21 14:28:53 -07:00
passant5 0c9e3a08fd
update caravel with tying `porb_h_in` with `por_l_in` (#326)
* update caravel with tying `porb_h_in` with `por_l_in` at the `mgmt_core_wrapper` in the top-level layout:
- `porb_h_in` shouldn't be left floating as it is an input to `clkbuf_16`

* add caravel-eco.gds (same as caravel.gds)
2022-10-21 11:52:00 -07:00
Jeff DiCorpo 4192c34f4b
Caravan redesign (#321)
* Fixed caravan top level power routing and updated views for mag, gds and lef

* caravan(rtl): updates

~ typos fix
- remove unused pin in chip_io_alt
+ add caravan_power_routing verilog

* Apply automatic changes to Manifest and README.rst

* ~ update caravan openlane configs to add extra cell references
~ correct placment and cell names of some macro in caravan interactive script

* reharden: caravan

+ add non functional blocks
+ add an initial iteration of caravan

* Apply automatic changes to Manifest and README.rst

* Revert "Fixed caravan top level power routing and updated views for mag, gds and lef"

This reverts commit 70628f748a.

* fixed caravan top level power routing

* reharden: caravan

based on new power routing
~ guard rtl chip_io power pins in the power macro guard

* Apply automatic changes to Manifest and README.rst

* fixed caravan top level power routing

* rehadren: caravan

+ add caravan signal routing to openlane run
~ change rtl to guard power and analog against routing by
openlane by ifndef TOP_ROUTING
~ add pr bounadry for caravan signal routing to fix origin issues

* Apply automatic changes to Manifest and README.rst

* fix power connection in buffering block and regenerate gl

* Apply automatic changes to Manifest and README.rst

* updated views for caravan

* Added extract unique to lvs-gds-cell target. (#313)

* This fixes errors in the top level RTL of caravan that failed to
hook up the buffers through the SoC correctly.

* Apply automatic changes to Manifest and README.rst

* reharden: caravan

~ rtl updated

* fixed caravan mag top level

* updated views for caravan + signoff

* fixed top level cell name

* fix syntax error related to signal initialization place in caravan (#319)

* fix syntax error related to signal initialization place in caravan- fixed in caravel in another commit

* Apply automatic changes to Manifest and README.rst

Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com>

* Apply automatic changes to Manifest and README.rst

Co-authored-by: Marwan Abbas <marwaneltoukhy@aucegypt.edu>
Co-authored-by: kareem <kareem.farid@efabless.com>
Co-authored-by: kareefardi <kareefardi@users.noreply.github.com>
Co-authored-by: Mitch Bailey <d-m-bailey@users.noreply.github.com>
Co-authored-by: Tim Edwards <tim@opencircuitdesign.com>
Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com>
Co-authored-by: Marwan Abbas <67271180+marwaneltoukhy@users.noreply.github.com>
Co-authored-by: M0stafaRady <107422726+M0stafaRady@users.noreply.github.com>
Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com>
Co-authored-by: jeffdi <jeffdi@users.noreply.github.com>
2022-10-21 07:37:41 -07:00
Marwan Abbas 71b1faabc5
Caravel final views (#310)
* added views for each step of generating final caravel.gds

* generated the right caravel and caravel-eco gds

* renamed caravel_signoff and removed caravel-non-eco

Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
2022-10-19 18:27:26 -07:00
Marwan Abbas bbb6bf775c
Caravel redesign new top (#300)
* reharden: caravel

~ shift caravel_clocking due to change in size
~ change the pr boundary of caravel_power_routing mag file
~ regenarate lef of caravel_power_routing

* update pdn for `caravel_clocking` & `digital_pll`

* added script to update and generate the power routing views

* ~ run update_power_routing_views from the caravel root with prboundary

* fix output message

* added power routing lef, mag and gds

* fix update_power_routing_views saving wrong cell name

* reharden: caravel

~ incorperate pdn changes
~ re-extract spefs

* fix caravel_power_routing views

* fix abs path in maglef views

* fix abs path in mag views
add substcut layers in gpio_control_block and mgmt_protect

* generate a new chip_io gds

* regenerate gpio_control_block due to mag and gds not in sync

* reharden: caravel

~ change config to pass clean routing
~ use updated views of macros

* lvs clean views

* add caravel top-level generated sdf for all corners

* fix absolute path for mgmt_core_wrapper

Co-authored-by: kareem <kareem.farid@efabless.com>
Co-authored-by: Bassant Hassan <bassant.hassan@efabless.com>
2022-10-18 17:24:07 -07:00
Marwan Abbas 1d3621c66a
Merge pull request #296 from efabless/chip_io_fixes_10_18_2022
Fixes to chip_io to fix LVS issues.  Also added back top level
2022-10-18 17:34:02 +02:00
Marwan Abbas 20e51c8504
Merge pull request #281 from efabless/fix_buffer_cell_for_lvs
Small change to the signal buffer layouts for LVS.
2022-10-18 17:12:49 +02:00
Marwan Abbas 981f0a54ff
Merge pull request #177 from efabless/top_layout_rework
Create top-level LEF and pin generation script.
2022-10-18 17:11:02 +02:00
Marwan Abbas 38902bde45
Merge pull request #292 from efabless/caravel-redesign-digital_pll-decaps
reharden: digital_pll
2022-10-18 16:35:49 +02:00
Marwan Abbas 4cbf8ca4f6
Merge pull request #291 from efabless/caravel-redesign-clocking-decaps
reharden: caravel_clocking
2022-10-18 16:35:26 +02:00
Tim Edwards 714fc1cd13 Fixes to chip_io to fix LVS issues. Also added back top level
pins on the pads, and reinstated the script that does that from
another branch that was not merged.
2022-10-18 10:29:43 -04:00
kareem 68063ddadc reharden: digital_pll
~ increase width for more spread decaps
+ add or cells to cell exclude
~ change placement density in accordance to area
~ change padding to allow for space for decaps
2022-10-18 07:07:32 -07:00
Marwan Abbas 7c468c0be2 Fixed PDN to incorprate new changes to housekeeping and caravel clocking 2022-10-18 15:52:47 +02:00
kareem fdeb6003f3 Merge branch 'caravel_redesign-digital_pll-no-or' into caravel_redesign 2022-10-18 06:31:00 -07:00
kareem 3bd586b50c reharden: caravel_clocking
~ increase height for more spread decap insertion
+ add or cells to cell exclude
~ adjust pdn to have an offset half to pitch
~ change placement density in accordance to area
~ change padding to allow for space for decap insertion
2022-10-18 06:18:30 -07:00
mo-hosni 1110ae2fe8 update housekeeping views and openlane configuration 2022-10-18 04:07:27 -07:00
Tim Edwards 6bed433856 One additional small change to the signal buffer layouts to avoid
a collision with the lower three right-hand side I/O cells that
was discovered by LVS.
2022-10-17 15:51:43 -04:00
kareem 712b784e16 reharden!: digital_pll
~ disable or gate
+ add nosynth list file
2022-10-17 12:33:25 -07:00
Mohamed Shalan c0db032dbf
Merge pull request #275 from efabless/gpio_control_block-fixes
Gpio control block fixes
2022-10-17 20:56:10 +02:00
Mohamed Shalan 3fbc52ecbf
Merge pull request #276 from efabless/caravel_redesign-digital_pll-fanout
reharden!: digital_pll
2022-10-17 20:50:01 +02:00
mo-hosni 2d147966b9 Update housekeeping views and openlane configuration 2022-10-17 11:37:24 -07:00
kareem e5d9788a43 reharden!: digital_pll
~ enable synth buffering to fix fanout
~ add *buf_1* to no synth list
~ add attribute (* keep *) to the oscillator as dont
touch for yosys

!need to verify that the oscillator remains untouched
2022-10-17 10:56:01 -07:00
kareem d241ca64c2 add substrateCut layer on top of gpio_logic_high in gpio_control_block 2022-10-17 10:25:04 -07:00
Marwan Abbas c524106fed
Merge pull request #263 from efabless/caravel_redesign-pdn-again
update caravel pdn
2022-10-17 16:12:01 +02:00
kareem d416d222b2 sync mag and lef with gds 2022-10-17 06:15:52 -07:00
kareem a8794dff4b reharden: caravel
~ reharden with updated pdn
~ add stubs for non functional blocks
2022-10-17 03:59:28 -07:00
kareem 394546731f update caravel pdn
~ change pr boundary to origin to (0,0)
~ sync lef and mag with gds
2022-10-17 03:51:21 -07:00
marwaneltoukhy 2d28c973ee added views for caravel with power routing 2022-10-16 19:08:56 -07:00
marwaneltoukhy 7ec1eeb010 Merge branch 'caravel_redesign' into caravel_redesign-top-level 2022-10-16 18:39:39 -07:00
Tim Edwards 69d353f65c Corrected the verilog and the layout for the caravan version of the
signal buffering (verilog was missing one of the buffers, and the
layout had some of the labels at the top accidentally erased).
2022-10-16 21:06:27 -04:00
kareem 2409207178 reharden: caravel
~ add non functional blocks - like caravel_motto
2022-10-16 15:44:27 -07:00
Tim Edwards f7e2dc80a6 Made a minor correction to the layout to remove an extra unused
buffer.  This does not affect ongoing top-level routing work, but
is needed for LVS.
2022-10-16 17:57:14 -04:00
kareem 704f19b6c7 reharden: caravel
~ correct placement for spare_logic_block
~ add changes from buffering macro
2022-10-16 12:56:41 -07:00
kareem 7ff92e121f Merge remote-tracking branch 'origin/fix_top_buffers_again' into caravel_redesign-top-level 2022-10-16 11:18:54 -07:00
Tim Edwards 48ae31205c Another change to the pin endpoint positions to make sure that they
have at least 0.28um spacing to the next wire.  Not sure that this
is going to solve the router errors, though.
2022-10-16 14:15:12 -04:00
kareem 2a3493ed65 Merge branch 'fix_top_buffers_again' into caravel_redesign-top-level 2022-10-16 10:03:54 -07:00
Tim Edwards c5e7c67d60 Once again. . . Rewrote the RTL verilog so that only signals
being buffered pass through the buffer macros.  Removed the
straight-through signals from the layout, and renumbered the
vectors in the buffer cells, which no longer match the numbering
at the top level (unfortunately).
2022-10-16 12:49:44 -04:00
kareem b9a2e697d5 Merge branch 'fix_top_buffers_again' into caravel_redesign-top-level 2022-10-16 08:00:37 -07:00
Tim Edwards 589f351dcb Additional modification to move pins up into an uncongested area
above housekeeping, because the upper GPIO pins are in the wrong
place relative to the new GPIO signal routing below the SoC.
Added pins for the pass-through connections.  Unconnected/
unrouted OEB pins are still not present and probably should be
removed from the RTL.
2022-10-16 10:52:53 -04:00
kareem 38e78abfd5 Merge branch 'fix_top_buffers_again' into caravel_redesign-top-level 2022-10-16 07:24:15 -07:00
Tim Edwards 43b8f9d4fe Merge branch 'caravel_redesign' into fix_top_buffers_again
Updating to the most recent caravel_redesign branch version.
2022-10-16 10:05:36 -04:00
kareem aa2dfe9421 Merge branch 'fix_top_buffers_again' of github.com:efabless/caravel into fix_top_buffers_again 2022-10-16 07:01:55 -07:00
kareem fc0701003c reharden: caravel
- based on second iteration of the buffer macro
- change config with updated placement of spare logic macros
and power routing cell
2022-10-16 06:58:46 -07:00
Tim Edwards dcc3c56b83 Some additional corrections to the gpio_signal_buffering cells.
Corrected one instance where a buffer had incorrectly been replaced
with a decap cell.  Moved the left-hand side in by 0.6um to clear
the chip_io connections on the left-hand side.  Corrected a small
DRC error in a route position at the bottom.
2022-10-16 09:50:20 -04:00
kareem f5a8382395 Merge branch 'caravel_redesign' into fix_top_buffers_again 2022-10-16 05:55:23 -07:00