* reharden: caravel
~ shift caravel_clocking due to change in size
~ change the pr boundary of caravel_power_routing mag file
~ regenarate lef of caravel_power_routing
* update pdn for `caravel_clocking` & `digital_pll`
* added script to update and generate the power routing views
* ~ run update_power_routing_views from the caravel root with prboundary
* fix output message
* added power routing lef, mag and gds
* fix update_power_routing_views saving wrong cell name
* reharden: caravel
~ incorperate pdn changes
~ re-extract spefs
* fix caravel_power_routing views
* fix abs path in maglef views
* fix abs path in mag views
add substcut layers in gpio_control_block and mgmt_protect
* generate a new chip_io gds
* regenerate gpio_control_block due to mag and gds not in sync
* reharden: caravel
~ change config to pass clean routing
~ use updated views of macros
* lvs clean views
* add caravel top-level generated sdf for all corners
* fix absolute path for mgmt_core_wrapper
Co-authored-by: kareem <kareem.farid@efabless.com>
Co-authored-by: Bassant Hassan <bassant.hassan@efabless.com>
Corrected one instance where a buffer had incorrectly been replaced
with a decap cell. Moved the left-hand side in by 0.6um to clear
the chip_io connections on the left-hand side. Corrected a small
DRC error in a route position at the bottom.
- primetime generated files (reports, lib, and sdf) are added to `./signoff/<design>/primetime-signoff/`
- STA logs are added to `./scripts/logs/<design>/`
establishes all the pin names, positions, classes, and uses. Adds
a script which uses the LEF abstract view to annotate the top level
layouts for caravel and caravan with the chip pins (not yet run---
waiting for a valid top level layout after top-level routing).
Also: Updated the copyright block to increase the chip version
number and update the date.
tweak blackbox lvs scripts for very fast extract; update spi/lvs/*.spice.
The .spice (once propagated to caravel-lite AND caravel-lite embed in mpw_precheck docker)
will pass the consistency check.
Co-authored-by: Risto Bell <rb@efabless.com>
* Modified the set_user_id.py script so that mode "-report" returns
a valid value, instead of throwing an error, because the "info.yaml"
file was removed without due consideration of the side effects.
* Apply automatic changes to Manifest and README.rst
Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com>
it will recognize all block cell types in the gate level netlist
after having been run previously. The former code was only looking
for numeric digits in the cell name, but the cell name suffix is
hex, not integer, and so the script needs to add a check for the
letters A-F or a-f in the cell name suffix. This is not an
immediate issue because the two default values used are "0403" and
"1803" and happen not to have any alphabetic hex digits. But if
it were deemed necessary to change a default, then this script
should not break.
* Create lvs-cvc.rst
* user_project_analog_wrapper -> user_analog_project_wrapper
* Added table
* Update lvs-cvc.rst
* Create lvs_cvc_mpw4.rst
Initial steps for LVS and CVC-RV for MPW-4 slot-002
* Update lvs_cvc_mpw4.rst
diode and short errors
* daily progress
`simple_por` changes to `caravel.v`
* Update lvs_cvc_mpw4.rst
* Changed int (truncate) to round to correct gpio_default error.
* Replace gpio_defaults_block for gpio 0-4 correctly.
Remove old versions of gpio_defaults_block 0403 and 1803.
* Removed local CVC-RV docs not ready for commit.
* Fixes an error in the gen_gpio_defaults.py script that is incompatible
with the use of indexed arrays for five of the gpio_defaults_block
instances. Previously this was handled by manually changing the names
in the layout file. This script avoids the need for manual modification
by directly handling the indexed notation. Also, this extends the
modifications made to the layout to include the first five defaults
blocks; otherwise, the first five defaults blocks are not changed and
the defaults will be wrong for the housekeeping SPI pins.
* Apply automatic changes to Manifest and README.rst
Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com>
* (1) Modified the .magicrc file to set a default for PDK if not set in the
environment. (2) Fixed the user ID programming layout to not leave holes
behind when the script moves the vias around (similar to the handling of
the GPIO defaults block). (3) Added substrate isolation to gpio_control_block
and fixed the path references to the standard cells. (4) Fixed the four
missing routes on the Caravan top level. (5) Reinstated the large rendered
labels for the pads on both caravel and caravan. (6) Corrected the top
level gate-level netlist for caravan to add the missing pins to the
management core wrapper. (7) Did the same for the caravan top level RTL.
(8) Created scripts to run full LVS including extracting the management
core wrapper and reading all gate-level verilog submodules. (9) Moved all
of the LVS scripts to the scripts directory.
* Apply automatic changes to Manifest and README.rst
* Made the changes from pull request #73 as they did not get merged
successfully, and if merged now they will generate conflicts with
this pull request in scripts/set_user_id.py. So it's easier to
just manually add them to this pull request.
* Apply automatic changes to Manifest and README.rst
Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com>
* Create lvs-cvc.rst
* user_project_analog_wrapper -> user_analog_project_wrapper
* Added table
* Update lvs-cvc.rst
* Create lvs_cvc_mpw4.rst
Initial steps for LVS and CVC-RV for MPW-4 slot-002
* Update lvs_cvc_mpw4.rst
diode and short errors
* daily progress
`simple_por` changes to `caravel.v`
* Update lvs_cvc_mpw4.rst
* Remove old local documentation.
* Changes that correct gpio_default_block, user_id_programming, and mgmt_core references.
mgmt_core_wrapper
Use absolute path instead of relative path.
user_id_programming
Remove GDS references as GDS is no longer modified.
Corrected string concatenation.
Corrected mag data replacement.
Corrected verilog data replacement.
gpio_default_block
Rename instances for gpio_default_blocks 0-4 in caravel.mag and caravan.mag.
Change replace range in gen_gpio_defaults.py to handle gpio_default_blocks 0-4.
* Revert changes related to gpio_default_block.
* Changed mgmt_core_wrapper absolute path from UPRJ_ROOT to MCW_ROOT.
* Corrected MCW_ROOT path (includes mgmt_core_wrapper)
getting changed by "make ship" because the build is done in a place
where the path pointer to the user_id_programming GDS still points
back to the original caravel repository, not the user project
repository. The user_id_programming GDS was removed (no longer used),
the user_id_programming.mag file was modified to remove the path
pointer to the GDS, and the set_user_id.py script was modified to
make changes directly to the user_id_programming.mag file instead of
the GDS. An additional method was added to the set_user_id.py script
to modify the gate-level verilog/gl/user_id_programming.v to make
the user ID correct for gate-level testbench simulations.
correctly no matter how the "gpio_defaults_block.mag" and
"gl/gpio_defaults_block.v" are defined. Previously it assumed
that they both defined all bits as zero, which was not the case
for the layout. Now both define bit value 0x0402 and the script
can flip bits either direction as needed in both verilog and
layout
verilog gate-level netlists to match the correct GPIO default
value assignments, and modify the top level gate-level caravel.v
and caravan.v netlists to match.
characters in the user_id_textblock layout, which was backwards,
and (2) add a path reference to "hexdigits" for each new character
layout encountered in the file, so that the text block layouts
are found even if "addpath hexdigits" has not been specified.
There were some other corrections to handling gzipped files that
probably does not apply in practice, where "make uncompress" has
been run prior to the set_user_id.py script.
so that it contains a valid layout after processing by Openlane (since the
verilog module is named gpio_defaults_block). Corrected the orientation of
the defaults block layouts on the right side of Caravel and erased the
incorrect routing there. Reinstated the copyright, user ID text, open source
logo, and Caravel logo. Revised the gen_gpio_defaults.py script to handle
the first five GPIOs in the same way as the others, although as fixed entries
which cannot be modified by the user project designer.
makes backup copies of caravel and caravan layouts and replaces the
cell name of any gpio defaults block that is changed from the
contents of user_defines.v. NOTE: user_defines.v ultimately must
reside in the user project. The Makefile should copy the user's
version into the caravel directory space before running the script,
or else the script should be rewritten to reference the user's
project area when reading user_defines.v.
verilog/rtl/, and creates all the layout files needed to represent
all unique combinations of defaults used in the file. Not done:
Modifying the top level layout to use the correct defaults (because
the top level layout does not yet exist).
R. Timothy Edwards
Kareem Farid
Marwan Abbas
Marwan Abbas
kareem
Passant
Mohamed Shalan
sto6
Mitch Bailey
jeffdi